Commit Graph

171 Commits

Author SHA1 Message Date
Jiri Denemark
3944f6855b cpu_map: Add Cooperlake x86 CPU model
The stepping range (10-11) is likely incomplete. QEMU uses 10 and the
CPUID data for Cooperlake show 11. We will update the range if needed
once more details about he CPU are available.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Pavel Hrdina <phrdina@redhat.com>
2020-05-25 19:20:21 +02:00
Jiri Denemark
12eb0c9496 cpu_map: Add pschange-mc-no bit in IA32_ARCH_CAPABILITIES MSR
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Pavel Hrdina <phrdina@redhat.com>
2020-05-25 19:20:21 +02:00
Jiri Denemark
58691208e2 cputest: Add data for Cooperlake CPU
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Pavel Hrdina <phrdina@redhat.com>
2020-05-25 19:20:21 +02:00
Jiri Denemark
6b50f54ca7 cputest: Add data for AMD Ryzen 9 3900X 12-Core Processor
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Michal Privoznik <mprivozn@redhat.com>
2020-05-13 18:30:45 +02:00
Jiri Denemark
5d6059f8ec cpu_map: Distinguish Cascadelake-Server from Skylake-Server
The signatures of these two CPU model differ only in stepping as both
report family 6 and model 85. Skylake-Server uses stepping 4 or less and
Cascadelake-Server uses stepping 5..7.

https://bugzilla.redhat.com/show_bug.cgi?id=1761678

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2020-04-08 17:52:50 +02:00
Jiri Denemark
3714779b15 cputest: Add data for Intel(R) Xeon(R) Gold 6130 CPU
Skylake-Server with family 6, model 85, stepping 4, which is currently
mis-detected as Cascadelake-Server CPU model.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2020-04-08 17:52:50 +02:00
Jiri Denemark
8605960389 cputest: Add data for Intel(R) Xeon(R) Platinum 9242 CPU
Cascadelake-Server with family 6, model 85, stepping 7.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2020-04-08 17:52:50 +02:00
Jiri Denemark
17cdefe5f1 cpu_map: Don't use new noTSX models for host-model CPUs
Host-model CPU definitions (and domain capabilities) will use the
original CPU models (without noTSX in their name) and explicitly disable
hle and rtm features. This way domains with host-model CPUs will be
migratable even to older versions of libvirt which do not support the
noTSX model variants.

The new models will be advertised in host capabilities and they may
be used explicitly with custom CPUs.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Tested-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
2020-03-25 22:27:39 +01:00
Christian Ehrhardt
dd17a4eba8 cpu_map: Add more -noTSX x86 CPU models
One of the mitigation methods for TAA[1] is to disable TSX
support on the host system.  Linux added a mechanism to disable
TSX globally through the kernel command line, and many Linux
distributions now default to tsx=off.  This makes existing CPU
models that have HLE and RTM enabled not usable anymore.

Add new versions of all CPU models that have the HLE and RTM
features enabled, that can be used when TSX is disabled in the
host system.

On systems disabling the features without those types defined
in cpu-maps users end up without modern CPU types in the list
of usable CPUs to use in the likes of virsh domcapabilities
or tools higher in the stack like virt-manager.

This adds:
-Cascadelake-Server-noTSX
-Icelake-Client-noTSX
-Icelake-Server-noTSX
-Skylake-Server-noTSX-IBRS
-Skylake-Client-noTSX-IBRS

Introduced in QEMU by commit v4.2.0-rc2-3-g9ab2237f19 (function)
                  and commit v4.2.0-rc2-4-g02fa60d101 (names)

References:

    [1] TAA, TSX asynchronous Abort:
        https://software.intel.com/security-software-guidance/insights/deep-dive-intel-transactional-synchronization-extensions-intel-tsx-asynchronous-abort
        https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html

Fixes: https://bugs.launchpad.net/ubuntu/+source/libvirt/+bug/1853200

Signed-off-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Message-Id: <20200310104806.2723-2-christian.ehrhardt@canonical.com>
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
2020-03-25 22:27:39 +01:00
Jiri Denemark
62a50628ff cputest: Add data for Intel(R) Core(TM) i7-8550U CPU without TSX
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
2020-03-09 16:17:34 +01:00
Daniel P. Berrangé
fbf27730a3 conf: add support for specifying CPU "dies" parameter
Recently CPU hardware vendors have started to support a new structure
inside the CPU package topology known as a "die". Thus the hierarchy
is now:

  sockets > dies > cores > threads

This adds support for "dies" in the XML parser, with the value
defaulting to 1 if not specified for backwards compatibility.

For example a system with 64 logical CPUs might report

   <topology sockets="4" dies="2" cores="4" threads="2"/>

Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2020-01-16 15:11:42 +00:00
Ani Sinha
1d17f881a2 cpu: add CLZERO CPUID support for AMD platforms
Qemu commit e900135dcfb67 ("i386: Add CPUID bit for CLZERO and XSAVEERPTR")
adds support for CLZERO CPUID bit.
This commit extends support for this CPUID bit into libvirt.

Signed-off-by: Ani Sinha <ani.sinha@nutanix.com>
Message-Id: <1575371352-99055-1-git-send-email-ani.sinha@nutanix.com>
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
2019-12-16 13:04:14 +01:00
Yingle Hou
153fcfd8d7 cputest: Add CPUID data for Hygon Dhyana 7185 32-core Processor
Add Hygon Dhyana CPU data test case related files.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Yingle Hou <houyingle@hygon.cn>
2019-12-13 13:05:01 +00:00
Daniel P. Berrangé
f0b3840fb6 build: only support python3 binary
python2 will be end of life by the time of the next
libvirt release. All our supported build targets, including
CentOS7, have a python3 build available.

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2019-12-04 13:13:01 +00:00
Jiri Denemark
af8e39921a cpu_conf: Don't format empty model for host-model CPUs
Most likely for historical reasons our CPU def formatting code is
happily adding useless <model fallback='allow'/> for host-model CPUs. We
can just drop it.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-11-25 15:29:19 +01:00
Jiri Denemark
9cd03f7957 cpu_map: Drop pconfig from Icelake-Server CPU model
The pconfig feature was enabled in QEMU by accident in 3.1.0. All other
newer versions do not support it and it was removed from the
Icelake-Server CPU model in QEMU.

We don't normally change our CPU models even when QEMU does so to avoid
breaking migrations between different versions of libvirt. But we can
safely do so in this specific case. QEMU never supported enabling
pconfig so any domain which was able to start has pconfig disabled.

With a small compatibility hack which explicitly disables pconfig when
CPU model equals Icelake-Server in migratable domain definition, only
one migration scenario stays broken (and there's nothing we can do about
it): from any host to a host with libvirt < 5.10.0 and QEMU > 3.1.0.

https://bugzilla.redhat.com/show_bug.cgi?id=1749672

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-11-12 20:14:16 +01:00
Jiri Denemark
6b4cc15730 cputest: Add data for Ice Lake Server CPU
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-11-12 20:14:16 +01:00
Daniel P. Berrangé
43d29cb40b python: sanitize spaces either side of operators
There should be a single space either side of operators. Inline
comments should have two spaces before the '#'

src/hyperv/hyperv_wmi_generator.py:130:45: E261 at least two spaces before inline comment
            source += '    { "", "", 0 },\n' # null terminated
                                            ^
src/esx/esx_vi_generator.py:417:25: E221 multiple spaces before operator
    FEATURE__DESERIALIZE  = (1 << 6)
                        ^
tests/cputestdata/cpu-cpuid.py:187:78: E225 missing whitespace around operator
                f.write("  <msr index='0x%x' edx='0x%08x' eax='0x%08x'/>\n" %(
                                                                             ^
docs/apibuild.py:524:47: E226 missing whitespace around arithmetic operator
                            self.line = line[i+2:]
                                              ^
...more...

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2019-11-11 14:24:19 +00:00
Daniel P. Berrangé
bc59247df9 python: sanitize blank line usage
Coding style expects 1 blank line between each method and 2 blank lines
before each class.

docs/apibuild.py:171:5: E303 too many blank lines (2)
    def set_header(self, header):
    ^
docs/apibuild.py:230:1: E302 expected 2 blank lines, found 1
class index:
^
docs/apibuild.py:175:5: E301 expected 1 blank line, found 0
    def set_module(self, module):
    ^
...more...

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2019-11-11 14:24:19 +00:00
Jiri Denemark
c8ec678fd9 cpu_map: Introduce IA32_ARCH_CAPABILITIES MSR features
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-06-20 14:02:36 +02:00
Jiri Denemark
538d873571 cpu_map: Define md-clear CPUID bit
CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091

The bit is set when microcode provides the mechanism to invoke a flush
of various exploitable CPU buffers by invoking the VERW instruction.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-05-14 19:33:37 +02:00
Jiri Denemark
5cd9db3ac1 cputest: Add data for Intel(R) Xeon(R) CPU E3-1225 v5
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-05-14 19:33:37 +02:00
Jiri Denemark
1c0ff5df07 cputest: Add support for MSR features to cpu-cpuid.py
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:40 +02:00
Jiri Denemark
8904492e21 cputest: Add support for MSR features to cpu-parse.sh
The script just parses whatever cpu-gather.sh printed out.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
ab3d6ea0da cputest: Add support for MSR features to cpu-gather.sh
This patch adds an inline python code for reading MSR features. Since
reading MSRs is a privileged operation, we have to read them from
/dev/cpu/*/msr if it is readable (i.e., the script runs as root) or
fallback to using KVM ioctl which can be done by any user that can start
virtual machines.

The python code is inlined rather than provided in a separate script
because whenever there's an issue with proper detection of CPU features,
we ask the reporter to run cpu-gather.sh script to give us all data we
need to know about the host CPU. Asking them to run several scripts
would likely result in one of them being ignored or forgotten.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
4dbb82a967 cputest: Generalize feature parsing in cpu-cpuid.py
The parseMapFeature for parsing features from CPU map XML can be easily
generalized to support more feature types.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
df9a23beee cputest: Prepare cpu-cpuid.py for MSR features
Let's make sure the current CPUID specific code is only applied to CPUID
features.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
6cbab502d3 cputest: Rename in_e[ac]x as e[ac]x_in in cpu-cpuid.py
This will let us simplify the code since the dictionary keys will match
attribute names in various XMLs.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
77f1fbaed8 cputest: Fix comparison in checkCPUIDFeature in cpu-cpuid.py
leaf["eax"] & eax > 0 check works correctly only if there's at most 1
bit set in eax. Luckily that's been always the case, but fixing this
could save us from future surprises.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
a7ad56edd9 cputest: Generalize function names in cpu-cpuid.py
The function will have to deal with both CPUID and MSR features.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
ee6185db02 cputest: Drop support for old QEMU from cpu-parse.sh
We don't really need to parse CPU data from QEMU older than 2.9 (i.e.,
before query-cpu-model-expansion) at this point. But even if there's a
need to do so, we can always use an older version of this script to do
the conversion.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
fcf4846a6b cpu_x86: Add support for storing MSR features in CPU map
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
2878278c74 cpu_map: Add Cascadelake-Server CPU model
Introduced in QEMU 3.1.0 by commit
c7a88b52f62b30c04158eeb07f73e3f72221b6a8

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
e024625735 cputest: Add data for Intel(R) Xeon(R) Platinum 8268 CPU
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
4ff74a806a cpu_map: Add more signatures for Broadwell CPU models
This fixes several CPUs which were incorrectly detected as
Skylake-Client.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-03-05 14:47:49 +01:00
Jiri Denemark
e89f877214 cpu_map: Add more signatures for Westmere CPU model
This fixes several CPUs which were incorrectly detected as a different
CPU model.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-03-05 14:47:49 +01:00
Jiri Denemark
dd08d27fc2 cputest: Test CPU signatures
The signature computation code is not too complicated and it will likely
never change so testing it is not very important. We do it mostly for a
nice side effect of easily accessible signature numbers for all CPU
data files.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-03-05 14:47:49 +01:00
Jiri Denemark
87a46f5d8f cputest: Add data for Intel(R) Core(TM) i7-8700
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-03-05 14:38:35 +01:00
Jiri Denemark
483679d48f cputest: Add data for Intel(R) Xeon(R) CPU E5-2650
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-03-05 14:38:03 +01:00
Jiri Denemark
60046a2365 cputest: Add data for Intel(R) Xeon(R) CPU E7540
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-03-05 14:38:03 +01:00
Jiri Denemark
cd11ea73d0 cputest: Add data for Intel(R) Core(TM) i7-7600U
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-03-05 14:38:03 +01:00
Jiri Denemark
8d068f3601 cputest: Add data for Intel(R) Xeon(R) CPU E5-2630 v4
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-03-05 14:38:03 +01:00
Jiri Denemark
dd7682dd12 cputest: Make sure generated files pass syntax-check
The tests/cputestdata/cpu-parse.sh would produce JSON files with QEMU
replies which wouldn't pass syntax-check. Let's fix this by not emitting
an extra new line after reformatting the JSON file.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-03-05 14:38:03 +01:00
Jiri Denemark
ac5d4e6cb0 cputest: Use python3 in CPU parser scripts
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-02-22 18:41:19 +01:00
Jiri Denemark
78b148c3c8 cputest: Adapt scripts to split cpu_map
The tests/cputestdata/cpu-parse.sh script has been broken since the
cpu_map.xml file was split into several XMLs.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-02-22 18:41:19 +01:00
Jiri Denemark
511df17aec cpu_map: Add support for arch-capabilities feature
The feature was added to QEMU in 3.1.0 and it is currently blocking
migration, which is expected to change in the future. Luckily 3.1.0 is
new enough to give us migratability hints on each feature via
query-cpu-model-expension, which means we don't need to use the
"migratable" attribute on the CPU map XML.

The kernel calls this feature arch_capabilities and RHEL/CentOS 7.* use
arch-facilities. Apparently some CPU test files were gathered with the
RHEL version of QEMU. Let's update the test files to avoid possible
confusion about the correct naming.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-01-10 16:39:57 +01:00
Jiri Denemark
eb1b551d21 cpu: Add support for "stibp" x86_64 feature
QEMU commit v3.1.0-4-g0e89165829
KVM patch: https://lore.kernel.org/lkml/20181205191956.31480-1-ehabkost@redhat.com/

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2018-12-17 17:27:32 +01:00
Jiri Denemark
9813081119 cpu_map: Add features for Icelake CPUs
QEMU commits:

    e37a5c7fa4 (v2.12.0)
        i386: Add Intel Processor Trace feature support

    c2f193b538 (v2.7.0)
        target-i386: Add support for UMIP and RDPID CPUID bits

    aff9e6e46a (v2.12.0)
        x86/cpu: Enable new SSE/AVX/AVX512 cpu features

    f77543772d (v2.9.0)
        x86: add AVX512_VPOPCNTDQ features

    5131dc433d (v3.1.0)
        i386: Add CPUID bit for PCONFIG

    59a80a19ca (v3.1.0)
        i386: Add CPUID bit for WBNOINVD

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
2018-09-19 14:05:59 +02:00
Nikolay Shirokovskiy
0c8f0fb653 cputest: New test for Intel Core i5-650
Signed-off-by: Nikolay Shirokovskiy <nshirokovskiy@virtuozzo.com>
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
2018-04-18 11:39:53 +02:00
Radostin Stoyanov
d65f487a91 python3: cpu-reformat: Use the print() function
Replace the print statement, that is only available in Py2, with a
print function that is available in both Py2 and Py3 and drop the
explicit python version in the shebang.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Radostin Stoyanov <rstoyanov1@gmail.com>
2018-03-20 12:13:36 +00:00