Commit Graph

6 Commits

Author SHA1 Message Date
Tim Wiederhake
877f609b8c cpu_map: Add missing feature "flush-l1d"
Signed-off-by: Tim Wiederhake <twiederh@redhat.com>
Reviewed-by: Michal Privoznik <mprivozn@redhat.com>
2023-05-26 08:43:06 +02:00
Cole Robinson
812edc95a3 conf: cpu: Add <signature family=X model=X stepping=X/>
Internally we already collect x86 host family + model + stepping
numeric values. This exposed them in capabilities CPU output.
Example:

$ sudo virsh capabilities | grep -A1 -B1 signature
      <microcode version='240'/>
      <signature family='6' model='94' stepping='3'/>
      <counter name='tsc' frequency='3408010000' scaling='no'/>

Users need to know these values to calculate an expected.
SEV-ES/SEV-SNP launch measurement.

Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Cole Robinson <crobinso@redhat.com>
2022-06-16 12:12:45 -04:00
Jiri Denemark
c8ec678fd9 cpu_map: Introduce IA32_ARCH_CAPABILITIES MSR features
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-06-20 14:02:36 +02:00
Jiri Denemark
538d873571 cpu_map: Define md-clear CPUID bit
CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091

The bit is set when microcode provides the mechanism to invoke a flush
of various exploitable CPU buffers by invoking the VERW instruction.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-05-14 19:33:37 +02:00
Jiri Denemark
2878278c74 cpu_map: Add Cascadelake-Server CPU model
Introduced in QEMU 3.1.0 by commit
c7a88b52f62b30c04158eeb07f73e3f72221b6a8

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00
Jiri Denemark
e024625735 cputest: Add data for Intel(R) Xeon(R) Platinum 8268 CPU
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-12 22:53:39 +02:00