libvirt/src/cpu_map
Tim Wiederhake f0a5cf4b8a cpu_map: Define and enable Snowridge model
Due to missing pdpe1gb support in the host CPU data, the CPU is still
incorrectly detected as Westmere-IBRS for host capabilities because we
don't have the option to disable features included in the base model
there.

Signed-off-by: Tim Wiederhake <twiederh@redhat.com>
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
2021-01-07 23:23:41 +01:00
..
arm_cortex-a53.xml cpu_map: Introduce ARM cpu models 2020-05-15 12:04:24 +02:00
arm_cortex-a57.xml cpu_map: Introduce ARM cpu models 2020-05-15 12:04:24 +02:00
arm_cortex-a72.xml cpu_map: Introduce ARM cpu models 2020-05-15 12:04:24 +02:00
arm_Falkor.xml cpu_map: Introduce ARM cpu models 2020-05-15 12:04:24 +02:00
arm_features.xml
arm_FT-2000plus.xml cpu_map: Add Phytium FT-2000+ and Tengyun-S2500 2020-11-19 11:33:52 +01:00
arm_Kunpeng-920.xml cpu_map: Introduce ARM cpu models 2020-05-15 12:04:24 +02:00
arm_Tengyun-S2500.xml cpu_map: Add Phytium FT-2000+ and Tengyun-S2500 2020-11-19 11:33:52 +01:00
arm_ThunderX299xx.xml cpu_map: Introduce ARM cpu models 2020-05-15 12:04:24 +02:00
arm_vendors.xml cpu_map: Add Phytium FT-2000+ and Tengyun-S2500 2020-11-19 11:33:52 +01:00
index.xml cpu_map: Define and enable Snowridge model 2021-01-07 23:23:41 +01:00
meson.build cpu_map: Define and enable Snowridge model 2021-01-07 23:23:41 +01:00
ppc64_POWER6.xml
ppc64_POWER7.xml
ppc64_POWER8.xml
ppc64_POWER9.xml
ppc64_POWERPC_e5500.xml
ppc64_POWERPC_e6500.xml
ppc64_vendors.xml
sync_qemu_i386.py cpu_map: sync_qemu_cpu_i386: Detect features missing in libvirt 2020-12-07 15:09:57 +01:00
x86_486.xml
x86_athlon.xml
x86_Broadwell-IBRS.xml
x86_Broadwell-noTSX-IBRS.xml
x86_Broadwell-noTSX.xml
x86_Broadwell.xml
x86_Cascadelake-Server-noTSX.xml cpu_map: Distinguish Cascadelake-Server from Skylake-Server 2020-04-08 17:52:50 +02:00
x86_Cascadelake-Server.xml cpu_map: Distinguish Cascadelake-Server from Skylake-Server 2020-04-08 17:52:50 +02:00
x86_Conroe.xml
x86_Cooperlake.xml cpu_map: Unify apostrophe and quotation mark usage 2020-11-03 17:10:26 +01:00
x86_core2duo.xml
x86_coreduo.xml
x86_cpu64-rhel5.xml
x86_cpu64-rhel6.xml
x86_Dhyana.xml cpu_map: Drop 'monitor' from modern x86 CPU models 2020-11-24 20:13:23 +01:00
x86_EPYC-IBPB.xml cpu_map: Drop 'monitor' from modern x86 CPU models 2020-11-24 20:13:23 +01:00
x86_EPYC-Rome.xml cpu_map: Remove monitor feature from EPYC-Rome 2020-10-08 09:58:44 +02:00
x86_EPYC.xml cpu_map: Drop 'monitor' from modern x86 CPU models 2020-11-24 20:13:23 +01:00
x86_features.xml cpu_map: Add support for split-lock-detect CPU feature 2021-01-07 23:23:31 +01:00
x86_Haswell-IBRS.xml
x86_Haswell-noTSX-IBRS.xml
x86_Haswell-noTSX.xml
x86_Haswell.xml
x86_Icelake-Client-noTSX.xml cpu_map: Don't use new noTSX models for host-model CPUs 2020-03-25 22:27:39 +01:00
x86_Icelake-Client.xml
x86_Icelake-Server-noTSX.xml cpu_map: Fix Icelake Server model number 2020-12-04 12:56:19 +01:00
x86_Icelake-Server.xml cpu_map: Fix Icelake Server model number 2020-12-04 12:56:19 +01:00
x86_IvyBridge-IBRS.xml
x86_IvyBridge.xml
x86_kvm32.xml
x86_kvm64.xml
x86_n270.xml
x86_Nehalem-IBRS.xml
x86_Nehalem.xml
x86_Opteron_G1.xml
x86_Opteron_G2.xml
x86_Opteron_G3.xml cpu_map: Drop 'monitor' from modern x86 CPU models 2020-11-24 20:13:23 +01:00
x86_Opteron_G4.xml
x86_Opteron_G5.xml
x86_Penryn.xml
x86_pentium2.xml
x86_pentium3.xml
x86_pentium.xml
x86_pentiumpro.xml
x86_phenom.xml
x86_qemu32.xml
x86_qemu64.xml
x86_SandyBridge-IBRS.xml
x86_SandyBridge.xml
x86_Skylake-Client-IBRS.xml
x86_Skylake-Client-noTSX-IBRS.xml cpu_map: Don't use new noTSX models for host-model CPUs 2020-03-25 22:27:39 +01:00
x86_Skylake-Client.xml
x86_Skylake-Server-IBRS.xml cpu_map: Distinguish Cascadelake-Server from Skylake-Server 2020-04-08 17:52:50 +02:00
x86_Skylake-Server-noTSX-IBRS.xml cpu_map: Distinguish Cascadelake-Server from Skylake-Server 2020-04-08 17:52:50 +02:00
x86_Skylake-Server.xml cpu_map: Distinguish Cascadelake-Server from Skylake-Server 2020-04-08 17:52:50 +02:00
x86_Snowridge.xml cpu_map: Define and enable Snowridge model 2021-01-07 23:23:41 +01:00
x86_vendors.xml
x86_Westmere-IBRS.xml
x86_Westmere.xml