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538d873571
CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091 The bit is set when microcode provides the mechanism to invoke a flush of various exploitable CPU buffers by invoking the VERW instruction. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
31 lines
747 B
XML
31 lines
747 B
XML
<cpu>
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<arch>x86_64</arch>
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<model>Skylake-Client-IBRS</model>
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<vendor>Intel</vendor>
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<feature name='ds'/>
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<feature name='acpi'/>
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<feature name='ss'/>
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<feature name='ht'/>
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<feature name='tm'/>
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<feature name='pbe'/>
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<feature name='dtes64'/>
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<feature name='monitor'/>
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<feature name='ds_cpl'/>
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<feature name='vmx'/>
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<feature name='smx'/>
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<feature name='est'/>
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<feature name='tm2'/>
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<feature name='xtpr'/>
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<feature name='pdcm'/>
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<feature name='osxsave'/>
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<feature name='tsc_adjust'/>
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<feature name='clflushopt'/>
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<feature name='intel-pt'/>
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<feature name='md-clear'/>
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<feature name='stibp'/>
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<feature name='ssbd'/>
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<feature name='xsaves'/>
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<feature name='pdpe1gb'/>
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<feature name='invtsc'/>
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</cpu>
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