mirror of
https://gitlab.com/libvirt/libvirt.git
synced 2024-07-31 05:57:16 +00:00
538d873571
CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091 The bit is set when microcode provides the mechanism to invoke a flush of various exploitable CPU buffers by invoking the VERW instruction. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
35 lines
858 B
XML
35 lines
858 B
XML
<cpu>
|
|
<arch>x86_64</arch>
|
|
<model>Cascadelake-Server</model>
|
|
<vendor>Intel</vendor>
|
|
<feature name='ds'/>
|
|
<feature name='acpi'/>
|
|
<feature name='ss'/>
|
|
<feature name='ht'/>
|
|
<feature name='tm'/>
|
|
<feature name='pbe'/>
|
|
<feature name='dtes64'/>
|
|
<feature name='monitor'/>
|
|
<feature name='ds_cpl'/>
|
|
<feature name='vmx'/>
|
|
<feature name='smx'/>
|
|
<feature name='est'/>
|
|
<feature name='tm2'/>
|
|
<feature name='xtpr'/>
|
|
<feature name='pdcm'/>
|
|
<feature name='dca'/>
|
|
<feature name='osxsave'/>
|
|
<feature name='tsc_adjust'/>
|
|
<feature name='cmt'/>
|
|
<feature name='intel-pt'/>
|
|
<feature name='pku'/>
|
|
<feature name='ospke'/>
|
|
<feature name='md-clear'/>
|
|
<feature name='stibp'/>
|
|
<feature name='arch-capabilities'/>
|
|
<feature name='xsaves'/>
|
|
<feature name='mbm_total'/>
|
|
<feature name='mbm_local'/>
|
|
<feature name='invtsc'/>
|
|
</cpu>
|