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libvirt/src/cpu_map
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Jiri Denemark 5d6059f8ec cpu_map: Distinguish Cascadelake-Server from Skylake-Server 
The signatures of these two CPU model differ only in stepping as both
report family 6 and model 85. Skylake-Server uses stepping 4 or less and
Cascadelake-Server uses stepping 5..7.

https://bugzilla.redhat.com/show_bug.cgi?id=1761678

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2020-04-08 17:52:50 +02:00
..
arm_features.xml
cpu_map: Introduce ARM CPU features
2019-11-07 16:09:16 +01:00
index.xml
cpu_map: Add more -noTSX x86 CPU models
2020-03-25 22:27:39 +01:00
Makefile.inc.am
cpu_map: Add more -noTSX x86 CPU models
2020-03-25 22:27:39 +01:00
ppc64_POWER6.xml
…
ppc64_POWER7.xml
…
ppc64_POWER8.xml
…
ppc64_POWER9.xml
…
ppc64_POWERPC_e5500.xml
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ppc64_POWERPC_e6500.xml
…
ppc64_vendors.xml
…
x86_486.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_athlon.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Broadwell-IBRS.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Broadwell-noTSX-IBRS.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Broadwell-noTSX.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Broadwell.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Cascadelake-Server-noTSX.xml
cpu_map: Distinguish Cascadelake-Server from Skylake-Server
2020-04-08 17:52:50 +02:00
x86_Cascadelake-Server.xml
cpu_map: Distinguish Cascadelake-Server from Skylake-Server
2020-04-08 17:52:50 +02:00
x86_Conroe.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_core2duo.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_coreduo.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_cpu64-rhel5.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_cpu64-rhel6.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Dhyana.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_EPYC-IBPB.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_EPYC.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_features.xml
cpu_map/x86: Add support for BFLOAT16 data type
2020-01-07 09:07:40 +01:00
x86_Haswell-IBRS.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Haswell-noTSX-IBRS.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Haswell-noTSX.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Haswell.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Icelake-Client-noTSX.xml
cpu_map: Don't use new noTSX models for host-model CPUs
2020-03-25 22:27:39 +01:00
x86_Icelake-Client.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Icelake-Server-noTSX.xml
cpu_map: Don't use new noTSX models for host-model CPUs
2020-03-25 22:27:39 +01:00
x86_Icelake-Server.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_IvyBridge-IBRS.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_IvyBridge.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_kvm32.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_kvm64.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_n270.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Nehalem-IBRS.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Nehalem.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Opteron_G1.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Opteron_G2.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Opteron_G3.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Opteron_G4.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Opteron_G5.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Penryn.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_pentium2.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_pentium3.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_pentium.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_pentiumpro.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_phenom.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_qemu32.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_qemu64.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_SandyBridge-IBRS.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_SandyBridge.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Skylake-Client-IBRS.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Skylake-Client-noTSX-IBRS.xml
cpu_map: Don't use new noTSX models for host-model CPUs
2020-03-25 22:27:39 +01:00
x86_Skylake-Client.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Skylake-Server-IBRS.xml
cpu_map: Distinguish Cascadelake-Server from Skylake-Server
2020-04-08 17:52:50 +02:00
x86_Skylake-Server-noTSX-IBRS.xml
cpu_map: Distinguish Cascadelake-Server from Skylake-Server
2020-04-08 17:52:50 +02:00
x86_Skylake-Server.xml
cpu_map: Distinguish Cascadelake-Server from Skylake-Server
2020-04-08 17:52:50 +02:00
x86_vendors.xml
cpu: Add new Dhyana CPU model
2019-12-13 13:05:00 +00:00
x86_Westmere-IBRS.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00
x86_Westmere.xml
cpu_map: Add <decode> element to x86 CPU model definitions
2020-03-25 22:27:39 +01:00