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4ad6a73bfc
We're only adding only info about L3 caches, we can add more
later (just by changing one line), but for now that's more than enough
without overwhelming anyone.
XML snippet of how this should look like (also seen as part of the commit):
<cache>
<bank id='0' level='3' type='both' size='8192' unit='KiB' cpus='0-7'/>
</cache>
Signed-off-by: Martin Kletzander <mkletzan@redhat.com>
37 lines
1.2 KiB
XML
37 lines
1.2 KiB
XML
<capabilities>
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<host>
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<cpu>
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<arch>x86_64</arch>
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</cpu>
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<power_management/>
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<migration_features>
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<live/>
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</migration_features>
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<topology>
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<cells num='1'>
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<cell id='0'>
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<memory unit='KiB'>1048576</memory>
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<pages unit='KiB' size='4'>2048</pages>
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<pages unit='KiB' size='2048'>4096</pages>
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<pages unit='KiB' size='1048576'>6144</pages>
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<cpus num='8'>
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<cpu id='0' socket_id='0' core_id='0' siblings='0,4'/>
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<cpu id='1' socket_id='0' core_id='1' siblings='1,5'/>
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<cpu id='2' socket_id='0' core_id='2' siblings='2,6'/>
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<cpu id='3' socket_id='0' core_id='3' siblings='3,7'/>
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<cpu id='4' socket_id='0' core_id='0' siblings='0,4'/>
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<cpu id='5' socket_id='0' core_id='1' siblings='1,5'/>
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<cpu id='6' socket_id='0' core_id='2' siblings='2,6'/>
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<cpu id='7' socket_id='0' core_id='3' siblings='3,7'/>
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</cpus>
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</cell>
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</cells>
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</topology>
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<cache>
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<bank id='0' level='3' type='both' size='8192' unit='KiB' cpus='0-7'/>
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</cache>
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</host>
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</capabilities>
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