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538d873571
CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091 The bit is set when microcode provides the mechanism to invoke a flush of various exploitable CPU buffers by invoking the VERW instruction. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
13 lines
481 B
XML
13 lines
481 B
XML
<cpu mode='custom' match='exact'>
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<model fallback='forbid'>Skylake-Client-IBRS</model>
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<vendor>Intel</vendor>
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<feature policy='require' name='ss'/>
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<feature policy='require' name='hypervisor'/>
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<feature policy='require' name='tsc_adjust'/>
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<feature policy='require' name='clflushopt'/>
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<feature policy='require' name='md-clear'/>
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<feature policy='require' name='stibp'/>
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<feature policy='require' name='ssbd'/>
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<feature policy='require' name='pdpe1gb'/>
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</cpu>
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