mirror of
https://gitlab.com/libvirt/libvirt.git
synced 2024-12-22 21:55:25 +00:00
538d873571
CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091 The bit is set when microcode provides the mechanism to invoke a flush of various exploitable CPU buffers by invoking the VERW instruction. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
34 lines
1.3 KiB
XML
34 lines
1.3 KiB
XML
<cpu mode='custom' match='exact'>
|
|
<model fallback='forbid'>Cascadelake-Server</model>
|
|
<vendor>Intel</vendor>
|
|
<feature policy='require' name='ds'/>
|
|
<feature policy='require' name='acpi'/>
|
|
<feature policy='require' name='ss'/>
|
|
<feature policy='require' name='ht'/>
|
|
<feature policy='require' name='tm'/>
|
|
<feature policy='require' name='pbe'/>
|
|
<feature policy='require' name='dtes64'/>
|
|
<feature policy='require' name='monitor'/>
|
|
<feature policy='require' name='ds_cpl'/>
|
|
<feature policy='require' name='vmx'/>
|
|
<feature policy='require' name='smx'/>
|
|
<feature policy='require' name='est'/>
|
|
<feature policy='require' name='tm2'/>
|
|
<feature policy='require' name='xtpr'/>
|
|
<feature policy='require' name='pdcm'/>
|
|
<feature policy='require' name='dca'/>
|
|
<feature policy='require' name='osxsave'/>
|
|
<feature policy='require' name='tsc_adjust'/>
|
|
<feature policy='require' name='cmt'/>
|
|
<feature policy='require' name='intel-pt'/>
|
|
<feature policy='require' name='pku'/>
|
|
<feature policy='require' name='ospke'/>
|
|
<feature policy='require' name='md-clear'/>
|
|
<feature policy='require' name='stibp'/>
|
|
<feature policy='require' name='arch-capabilities'/>
|
|
<feature policy='require' name='xsaves'/>
|
|
<feature policy='require' name='mbm_total'/>
|
|
<feature policy='require' name='mbm_local'/>
|
|
<feature policy='require' name='invtsc'/>
|
|
</cpu>
|