2019-04-18 17:32:41 +00:00
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// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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2019-05-08 10:22:53 +00:00
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// found in the LICENSE-BSD-3-Clause file.
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//
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// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
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2019-04-18 17:32:41 +00:00
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extern crate devices;
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2019-09-11 16:07:33 +00:00
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#[cfg(feature = "pci_support")]
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2019-04-18 17:32:41 +00:00
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extern crate pci;
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extern crate vm_allocator;
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extern crate vm_memory;
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extern crate vmm_sys_util;
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2019-12-31 10:49:11 +00:00
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use arc_swap::ArcSwap;
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use devices::BusDevice;
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use libc::EFD_NONBLOCK;
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use pci::{
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2019-10-28 17:50:32 +00:00
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BarReprogrammingParams, InterruptDelivery, InterruptParameters, MsixCap, MsixConfig,
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PciBarConfiguration, PciBarRegionType, PciCapability, PciCapabilityID, PciClassCode,
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PciConfiguration, PciDevice, PciDeviceError, PciHeaderType, PciInterruptPin,
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PciMassStorageSubclass, PciNetworkControllerSubclass, PciSubclass,
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};
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use std::any::Any;
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use std::result;
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use std::sync::atomic::{AtomicU16, AtomicUsize, Ordering};
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use std::sync::{Arc, Mutex};
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use vm_allocator::SystemAllocator;
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2019-11-19 00:42:31 +00:00
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use vm_device::{Migratable, MigratableError, Pausable, Snapshotable};
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use vm_memory::{Address, ByteValued, GuestAddress, GuestMemoryMmap, GuestUsize, Le32};
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use vmm_sys_util::{errno::Result, eventfd::EventFd};
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use super::VirtioPciCommonConfig;
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2019-10-30 18:03:02 +00:00
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use crate::transport::VirtioTransport;
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use crate::{
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Queue, VirtioDevice, VirtioDeviceType, VirtioInterrupt, VirtioInterruptType,
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VirtioIommuRemapping, DEVICE_ACKNOWLEDGE, DEVICE_DRIVER, DEVICE_DRIVER_OK, DEVICE_FAILED,
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DEVICE_FEATURES_OK, DEVICE_INIT, INTERRUPT_STATUS_CONFIG_CHANGED, INTERRUPT_STATUS_USED_RING,
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VIRTIO_MSI_NO_VECTOR,
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};
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#[allow(clippy::enum_variant_names)]
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enum PciCapabilityType {
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CommonConfig = 1,
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NotifyConfig = 2,
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IsrConfig = 3,
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DeviceConfig = 4,
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PciConfig = 5,
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SharedMemoryConfig = 8,
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}
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#[allow(dead_code)]
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#[repr(packed)]
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#[derive(Clone, Copy, Default)]
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struct VirtioPciCap {
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cap_len: u8, // Generic PCI field: capability length
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cfg_type: u8, // Identifies the structure.
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pci_bar: u8, // Where to find it.
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id: u8, // Multiple capabilities of the same type
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padding: [u8; 2], // Pad to full dword.
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offset: Le32, // Offset within bar.
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length: Le32, // Length of the structure, in bytes.
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}
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// It is safe to implement ByteValued. All members are simple numbers and any value is valid.
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unsafe impl ByteValued for VirtioPciCap {}
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impl PciCapability for VirtioPciCap {
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fn bytes(&self) -> &[u8] {
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self.as_slice()
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}
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fn id(&self) -> PciCapabilityID {
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PciCapabilityID::VendorSpecific
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}
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}
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2019-08-06 21:23:56 +00:00
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const VIRTIO_PCI_CAP_LEN_OFFSET: u8 = 2;
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impl VirtioPciCap {
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pub fn new(cfg_type: PciCapabilityType, pci_bar: u8, offset: u32, length: u32) -> Self {
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VirtioPciCap {
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cap_len: (std::mem::size_of::<VirtioPciCap>() as u8) + VIRTIO_PCI_CAP_LEN_OFFSET,
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cfg_type: cfg_type as u8,
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pci_bar,
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id: 0,
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padding: [0; 2],
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offset: Le32::from(offset),
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length: Le32::from(length),
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}
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}
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}
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#[allow(dead_code)]
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#[repr(packed)]
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#[derive(Clone, Copy, Default)]
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struct VirtioPciNotifyCap {
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cap: VirtioPciCap,
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notify_off_multiplier: Le32,
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}
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// It is safe to implement ByteValued. All members are simple numbers and any value is valid.
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unsafe impl ByteValued for VirtioPciNotifyCap {}
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impl PciCapability for VirtioPciNotifyCap {
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fn bytes(&self) -> &[u8] {
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self.as_slice()
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}
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fn id(&self) -> PciCapabilityID {
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PciCapabilityID::VendorSpecific
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}
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}
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impl VirtioPciNotifyCap {
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pub fn new(
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cfg_type: PciCapabilityType,
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pci_bar: u8,
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offset: u32,
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length: u32,
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multiplier: Le32,
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) -> Self {
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VirtioPciNotifyCap {
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cap: VirtioPciCap {
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cap_len: (std::mem::size_of::<VirtioPciNotifyCap>() as u8)
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+ VIRTIO_PCI_CAP_LEN_OFFSET,
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cfg_type: cfg_type as u8,
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pci_bar,
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id: 0,
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padding: [0; 2],
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offset: Le32::from(offset),
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length: Le32::from(length),
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},
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notify_off_multiplier: multiplier,
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}
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}
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}
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2019-08-05 23:26:21 +00:00
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#[allow(dead_code)]
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#[repr(packed)]
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#[derive(Clone, Copy, Default)]
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struct VirtioPciCap64 {
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cap: VirtioPciCap,
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offset_hi: Le32,
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length_hi: Le32,
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}
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// It is safe to implement ByteValued. All members are simple numbers and any value is valid.
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unsafe impl ByteValued for VirtioPciCap64 {}
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impl PciCapability for VirtioPciCap64 {
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fn bytes(&self) -> &[u8] {
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self.as_slice()
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}
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fn id(&self) -> PciCapabilityID {
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PciCapabilityID::VendorSpecific
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}
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}
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impl VirtioPciCap64 {
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pub fn new(cfg_type: PciCapabilityType, pci_bar: u8, id: u8, offset: u64, length: u64) -> Self {
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VirtioPciCap64 {
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cap: VirtioPciCap {
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cap_len: (std::mem::size_of::<VirtioPciCap64>() as u8) + VIRTIO_PCI_CAP_LEN_OFFSET,
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cfg_type: cfg_type as u8,
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pci_bar,
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id,
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padding: [0; 2],
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offset: Le32::from(offset as u32),
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length: Le32::from(length as u32),
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},
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offset_hi: Le32::from((offset >> 32) as u32),
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length_hi: Le32::from((length >> 32) as u32),
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}
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}
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}
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#[allow(dead_code)]
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#[derive(Copy, Clone)]
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pub enum PciVirtioSubclass {
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NonTransitionalBase = 0xff,
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}
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impl PciSubclass for PciVirtioSubclass {
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fn get_register_value(&self) -> u8 {
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*self as u8
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}
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}
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// Allocate one bar for the structs pointed to by the capability structures.
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2019-06-06 17:15:10 +00:00
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// As per the PCI specification, because the same BAR shares MSI-X and non
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// MSI-X structures, it is recommended to use 8KiB alignment for all those
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// structures.
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const COMMON_CONFIG_BAR_OFFSET: u64 = 0x0000;
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const COMMON_CONFIG_SIZE: u64 = 56;
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const ISR_CONFIG_BAR_OFFSET: u64 = 0x2000;
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const ISR_CONFIG_SIZE: u64 = 1;
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const DEVICE_CONFIG_BAR_OFFSET: u64 = 0x4000;
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const DEVICE_CONFIG_SIZE: u64 = 0x1000;
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const NOTIFICATION_BAR_OFFSET: u64 = 0x6000;
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const NOTIFICATION_SIZE: u64 = 0x1000;
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const MSIX_TABLE_BAR_OFFSET: u64 = 0x8000;
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// The size is 256KiB because the table can hold up to 2048 entries, with each
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// entry being 128 bits (4 DWORDS).
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const MSIX_TABLE_SIZE: u64 = 0x40000;
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const MSIX_PBA_BAR_OFFSET: u64 = 0x48000;
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// The size is 2KiB because the Pending Bit Array has one bit per vector and it
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// can support up to 2048 vectors.
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const MSIX_PBA_SIZE: u64 = 0x800;
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// The BAR size must be a power of 2.
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const CAPABILITY_BAR_SIZE: u64 = 0x80000;
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const NOTIFY_OFF_MULTIPLIER: u32 = 4; // A dword per notification address.
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const VIRTIO_PCI_VENDOR_ID: u16 = 0x1af4;
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const VIRTIO_PCI_DEVICE_ID_BASE: u16 = 0x1040; // Add to device type to get device ID.
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pub struct VirtioPciDevice {
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// PCI configuration registers.
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configuration: PciConfiguration,
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// virtio PCI common configuration
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common_config: VirtioPciCommonConfig,
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// MSI-X config
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msix_config: Option<Arc<Mutex<MsixConfig>>>,
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// Number of MSI-X vectors
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msix_num: u16,
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// Virtio device reference and status
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device: Arc<Mutex<dyn VirtioDevice>>,
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device_activated: bool,
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// PCI interrupts.
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interrupt_status: Arc<AtomicUsize>,
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interrupt_cb: Option<Arc<VirtioInterrupt>>,
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// virtio queues
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queues: Vec<Queue>,
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queue_evts: Vec<EventFd>,
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// Guest memory
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memory: Option<Arc<ArcSwap<GuestMemoryMmap>>>,
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// Setting PCI BAR
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settings_bar: u8,
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// Whether to use 64-bit bar location or 32-bit
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use_64bit_bar: bool,
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}
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impl VirtioPciDevice {
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/// Constructs a new PCI transport for the given virtio device.
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pub fn new(
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memory: Arc<ArcSwap<GuestMemoryMmap>>,
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device: Arc<Mutex<dyn VirtioDevice>>,
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msix_num: u16,
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iommu_mapping_cb: Option<Arc<VirtioIommuRemapping>>,
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) -> Result<Self> {
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let device_clone = device.clone();
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let locked_device = device_clone.lock().unwrap();
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let mut queue_evts = Vec::new();
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for _ in locked_device.queue_max_sizes().iter() {
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queue_evts.push(EventFd::new(EFD_NONBLOCK)?)
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}
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let queues = locked_device
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.queue_max_sizes()
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.iter()
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.map(|&s| {
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let mut queue = Queue::new(s);
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queue.iommu_mapping_cb = iommu_mapping_cb.clone();
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queue
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})
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.collect();
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let pci_device_id = VIRTIO_PCI_DEVICE_ID_BASE + locked_device.device_type() as u16;
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let (msix_config, msix_config_clone) = if msix_num > 0 {
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let msix_config = Arc::new(Mutex::new(MsixConfig::new(msix_num)));
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let msix_config_clone = msix_config.clone();
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(Some(msix_config), Some(msix_config_clone))
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} else {
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(None, None)
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};
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2019-06-07 01:46:11 +00:00
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2019-09-17 16:34:51 +00:00
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// All device types *except* virtio block devices should be allocated a 64-bit bar
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// The block devices should be given a 32-bit BAR so that they are easily accessible
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// to firmware without requiring excessive identity mapping.
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let mut use_64bit_bar = true;
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let (class, subclass) = match VirtioDeviceType::from(locked_device.device_type()) {
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VirtioDeviceType::TYPE_NET => (
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PciClassCode::NetworkController,
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&PciNetworkControllerSubclass::EthernetController as &dyn PciSubclass,
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),
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VirtioDeviceType::TYPE_BLOCK => {
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use_64bit_bar = false;
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(
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PciClassCode::MassStorage,
|
|
|
|
&PciMassStorageSubclass::MassStorage as &dyn PciSubclass,
|
|
|
|
)
|
|
|
|
}
|
2019-07-02 15:16:11 +00:00
|
|
|
_ => (
|
|
|
|
PciClassCode::Other,
|
2019-08-15 15:41:40 +00:00
|
|
|
&PciVirtioSubclass::NonTransitionalBase as &dyn PciSubclass,
|
2019-07-02 15:16:11 +00:00
|
|
|
),
|
|
|
|
};
|
|
|
|
|
2019-04-18 17:32:41 +00:00
|
|
|
let configuration = PciConfiguration::new(
|
|
|
|
VIRTIO_PCI_VENDOR_ID,
|
|
|
|
pci_device_id,
|
2019-07-02 15:16:11 +00:00
|
|
|
class,
|
|
|
|
subclass,
|
2019-04-18 17:32:41 +00:00
|
|
|
None,
|
|
|
|
PciHeaderType::Device,
|
|
|
|
VIRTIO_PCI_VENDOR_ID,
|
|
|
|
pci_device_id,
|
2019-06-07 16:19:46 +00:00
|
|
|
msix_config_clone,
|
2019-04-18 17:32:41 +00:00
|
|
|
);
|
|
|
|
|
|
|
|
Ok(VirtioPciDevice {
|
|
|
|
configuration,
|
|
|
|
common_config: VirtioPciCommonConfig {
|
|
|
|
driver_status: 0,
|
|
|
|
config_generation: 0,
|
|
|
|
device_feature_select: 0,
|
|
|
|
driver_feature_select: 0,
|
|
|
|
queue_select: 0,
|
2019-07-26 18:48:07 +00:00
|
|
|
msix_config: Arc::new(AtomicU16::new(0)),
|
2019-04-18 17:32:41 +00:00
|
|
|
},
|
2019-06-07 01:46:11 +00:00
|
|
|
msix_config,
|
2019-05-29 23:33:29 +00:00
|
|
|
msix_num,
|
2019-04-18 17:32:41 +00:00
|
|
|
device,
|
|
|
|
device_activated: false,
|
|
|
|
interrupt_status: Arc::new(AtomicUsize::new(0)),
|
2019-06-03 20:57:26 +00:00
|
|
|
interrupt_cb: None,
|
2019-04-18 17:32:41 +00:00
|
|
|
queues,
|
|
|
|
queue_evts,
|
|
|
|
memory: Some(memory),
|
|
|
|
settings_bar: 0,
|
2019-09-17 16:34:51 +00:00
|
|
|
use_64bit_bar,
|
2019-04-18 17:32:41 +00:00
|
|
|
})
|
|
|
|
}
|
|
|
|
|
2019-05-06 17:27:40 +00:00
|
|
|
/// Gets the list of queue events that must be triggered whenever the VM writes to
|
|
|
|
/// `virtio::NOTIFY_REG_OFFSET` past the MMIO base. Each event must be triggered when the
|
|
|
|
/// value being written equals the index of the event in this list.
|
2019-10-30 18:03:02 +00:00
|
|
|
fn queue_evts(&self) -> &[EventFd] {
|
2019-05-06 17:27:40 +00:00
|
|
|
self.queue_evts.as_slice()
|
|
|
|
}
|
|
|
|
|
2019-04-18 17:32:41 +00:00
|
|
|
fn is_driver_ready(&self) -> bool {
|
|
|
|
let ready_bits =
|
|
|
|
(DEVICE_ACKNOWLEDGE | DEVICE_DRIVER | DEVICE_DRIVER_OK | DEVICE_FEATURES_OK) as u8;
|
|
|
|
self.common_config.driver_status == ready_bits
|
|
|
|
&& self.common_config.driver_status & DEVICE_FAILED as u8 == 0
|
|
|
|
}
|
|
|
|
|
2019-05-08 14:59:39 +00:00
|
|
|
/// Determines if the driver has requested the device (re)init / reset itself
|
|
|
|
fn is_driver_init(&self) -> bool {
|
|
|
|
self.common_config.driver_status == DEVICE_INIT as u8
|
|
|
|
}
|
|
|
|
|
2019-04-18 17:32:41 +00:00
|
|
|
fn are_queues_valid(&self) -> bool {
|
|
|
|
if let Some(mem) = self.memory.as_ref() {
|
2019-12-31 10:49:11 +00:00
|
|
|
self.queues.iter().all(|q| q.is_valid(mem.load().as_ref()))
|
2019-04-18 17:32:41 +00:00
|
|
|
} else {
|
|
|
|
false
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-10-30 16:13:29 +00:00
|
|
|
pub fn config_bar_addr(&self) -> u64 {
|
|
|
|
self.configuration.get_bar_addr(self.settings_bar as usize)
|
|
|
|
}
|
|
|
|
|
2019-04-18 17:32:41 +00:00
|
|
|
fn add_pci_capabilities(
|
|
|
|
&mut self,
|
|
|
|
settings_bar: u8,
|
|
|
|
) -> std::result::Result<(), PciDeviceError> {
|
|
|
|
// Add pointers to the different configuration structures from the PCI capabilities.
|
|
|
|
let common_cap = VirtioPciCap::new(
|
|
|
|
PciCapabilityType::CommonConfig,
|
|
|
|
settings_bar,
|
|
|
|
COMMON_CONFIG_BAR_OFFSET as u32,
|
|
|
|
COMMON_CONFIG_SIZE as u32,
|
|
|
|
);
|
|
|
|
self.configuration
|
|
|
|
.add_capability(&common_cap)
|
|
|
|
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
|
|
|
|
|
|
|
let isr_cap = VirtioPciCap::new(
|
|
|
|
PciCapabilityType::IsrConfig,
|
|
|
|
settings_bar,
|
|
|
|
ISR_CONFIG_BAR_OFFSET as u32,
|
|
|
|
ISR_CONFIG_SIZE as u32,
|
|
|
|
);
|
|
|
|
self.configuration
|
|
|
|
.add_capability(&isr_cap)
|
|
|
|
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
|
|
|
|
|
|
|
// TODO(dgreid) - set based on device's configuration size?
|
|
|
|
let device_cap = VirtioPciCap::new(
|
|
|
|
PciCapabilityType::DeviceConfig,
|
|
|
|
settings_bar,
|
|
|
|
DEVICE_CONFIG_BAR_OFFSET as u32,
|
|
|
|
DEVICE_CONFIG_SIZE as u32,
|
|
|
|
);
|
|
|
|
self.configuration
|
|
|
|
.add_capability(&device_cap)
|
|
|
|
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
|
|
|
|
|
|
|
let notify_cap = VirtioPciNotifyCap::new(
|
|
|
|
PciCapabilityType::NotifyConfig,
|
|
|
|
settings_bar,
|
|
|
|
NOTIFICATION_BAR_OFFSET as u32,
|
|
|
|
NOTIFICATION_SIZE as u32,
|
|
|
|
Le32::from(NOTIFY_OFF_MULTIPLIER),
|
|
|
|
);
|
|
|
|
self.configuration
|
|
|
|
.add_capability(¬ify_cap)
|
|
|
|
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
|
|
|
|
|
|
|
//TODO(dgreid) - How will the configuration_cap work?
|
|
|
|
let configuration_cap = VirtioPciCap::new(PciCapabilityType::PciConfig, 0, 0, 0);
|
|
|
|
self.configuration
|
|
|
|
.add_capability(&configuration_cap)
|
|
|
|
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
|
|
|
|
2019-06-07 16:19:46 +00:00
|
|
|
if self.msix_config.is_some() {
|
|
|
|
let msix_cap = MsixCap::new(
|
|
|
|
settings_bar,
|
|
|
|
self.msix_num,
|
|
|
|
MSIX_TABLE_BAR_OFFSET as u32,
|
2019-07-17 00:19:21 +00:00
|
|
|
settings_bar,
|
2019-06-07 16:19:46 +00:00
|
|
|
MSIX_PBA_BAR_OFFSET as u32,
|
|
|
|
);
|
|
|
|
self.configuration
|
|
|
|
.add_capability(&msix_cap)
|
|
|
|
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
|
|
|
}
|
2019-05-29 23:33:29 +00:00
|
|
|
|
2019-04-18 17:32:41 +00:00
|
|
|
self.settings_bar = settings_bar;
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-10-30 18:03:02 +00:00
|
|
|
impl VirtioTransport for VirtioPciDevice {
|
|
|
|
fn ioeventfds(&self, base_addr: u64) -> Vec<(&EventFd, u64)> {
|
|
|
|
let notify_base = base_addr + NOTIFICATION_BAR_OFFSET;
|
|
|
|
self.queue_evts()
|
|
|
|
.iter()
|
|
|
|
.enumerate()
|
|
|
|
.map(|(i, event)| {
|
|
|
|
(
|
|
|
|
event,
|
|
|
|
notify_base + i as u64 * u64::from(NOTIFY_OFF_MULTIPLIER),
|
|
|
|
)
|
|
|
|
})
|
|
|
|
.collect()
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-04-18 17:32:41 +00:00
|
|
|
impl PciDevice for VirtioPciDevice {
|
2019-06-05 16:53:24 +00:00
|
|
|
fn assign_pin_irq(
|
|
|
|
&mut self,
|
|
|
|
irq_cb: Arc<InterruptDelivery>,
|
|
|
|
irq_num: u32,
|
|
|
|
irq_pin: PciInterruptPin,
|
|
|
|
) {
|
2019-04-18 17:32:41 +00:00
|
|
|
self.configuration.set_irq(irq_num as u8, irq_pin);
|
2019-06-03 20:57:26 +00:00
|
|
|
|
2019-07-26 18:48:07 +00:00
|
|
|
let interrupt_status = self.interrupt_status.clone();
|
|
|
|
let cb = Arc::new(Box::new(
|
|
|
|
move |int_type: &VirtioInterruptType, _queue: Option<&Queue>| {
|
|
|
|
let param = InterruptParameters { msix: None };
|
|
|
|
|
|
|
|
let status = match int_type {
|
|
|
|
VirtioInterruptType::Config => INTERRUPT_STATUS_CONFIG_CHANGED,
|
|
|
|
VirtioInterruptType::Queue => INTERRUPT_STATUS_USED_RING,
|
|
|
|
};
|
|
|
|
interrupt_status.fetch_or(status as usize, Ordering::SeqCst);
|
|
|
|
|
|
|
|
(irq_cb)(param)
|
|
|
|
},
|
|
|
|
) as VirtioInterrupt);
|
2019-06-03 20:57:26 +00:00
|
|
|
|
|
|
|
self.interrupt_cb = Some(cb);
|
2019-04-18 17:32:41 +00:00
|
|
|
}
|
|
|
|
|
2019-06-05 16:53:24 +00:00
|
|
|
fn assign_msix(&mut self, msi_cb: Arc<InterruptDelivery>) {
|
2019-06-07 16:19:46 +00:00
|
|
|
if let Some(msix_config) = &self.msix_config {
|
|
|
|
msix_config
|
|
|
|
.lock()
|
|
|
|
.unwrap()
|
|
|
|
.register_interrupt_cb(msi_cb.clone());
|
|
|
|
|
|
|
|
let msix_config_clone = msix_config.clone();
|
|
|
|
|
2019-07-26 18:48:07 +00:00
|
|
|
let common_config_msi_vector = self.common_config.msix_config.clone();
|
|
|
|
let cb = Arc::new(Box::new(
|
|
|
|
move |int_type: &VirtioInterruptType, queue: Option<&Queue>| {
|
|
|
|
let vector = match int_type {
|
|
|
|
VirtioInterruptType::Config => {
|
|
|
|
common_config_msi_vector.load(Ordering::SeqCst)
|
|
|
|
}
|
|
|
|
VirtioInterruptType::Queue => {
|
|
|
|
if let Some(q) = queue {
|
|
|
|
q.vector
|
|
|
|
} else {
|
|
|
|
0
|
|
|
|
}
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2019-12-11 08:09:16 +00:00
|
|
|
if vector == VIRTIO_MSI_NO_VECTOR {
|
|
|
|
return Ok(());
|
|
|
|
}
|
|
|
|
|
2019-07-26 18:48:07 +00:00
|
|
|
let config = &mut msix_config_clone.lock().unwrap();
|
|
|
|
let entry = &config.table_entries[vector as usize];
|
|
|
|
|
2019-08-08 15:43:59 +00:00
|
|
|
// If MSI-X interrupts are not enabled for this device, then simply
|
|
|
|
// ignore the interrupt.
|
|
|
|
if !config.enabled() {
|
|
|
|
return Ok(());
|
|
|
|
}
|
|
|
|
|
2019-07-26 18:48:07 +00:00
|
|
|
// In case the vector control register associated with the entry
|
|
|
|
// has its first bit set, this means the vector is masked and the
|
|
|
|
// device should not inject the interrupt.
|
|
|
|
// Instead, the Pending Bit Array table is updated to reflect there
|
|
|
|
// is a pending interrupt for this specific vector.
|
|
|
|
if config.masked() || entry.masked() {
|
|
|
|
config.set_pba_bit(vector, false);
|
|
|
|
return Ok(());
|
|
|
|
}
|
|
|
|
|
|
|
|
(msi_cb)(InterruptParameters { msix: Some(entry) })
|
|
|
|
},
|
|
|
|
) as VirtioInterrupt);
|
2019-05-29 23:33:29 +00:00
|
|
|
|
2019-06-07 16:19:46 +00:00
|
|
|
self.interrupt_cb = Some(cb);
|
|
|
|
}
|
2019-05-29 23:33:29 +00:00
|
|
|
}
|
|
|
|
|
2019-06-05 09:24:18 +00:00
|
|
|
fn write_config_register(&mut self, reg_idx: usize, offset: u64, data: &[u8]) {
|
|
|
|
self.configuration
|
|
|
|
.write_config_register(reg_idx, offset, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
fn read_config_register(&self, reg_idx: usize) -> u32 {
|
|
|
|
self.configuration.read_reg(reg_idx)
|
|
|
|
}
|
|
|
|
|
2019-10-28 17:50:32 +00:00
|
|
|
fn detect_bar_reprogramming(
|
|
|
|
&mut self,
|
|
|
|
reg_idx: usize,
|
|
|
|
data: &[u8],
|
|
|
|
) -> Option<BarReprogrammingParams> {
|
|
|
|
self.configuration.detect_bar_reprogramming(reg_idx, data)
|
|
|
|
}
|
|
|
|
|
2019-04-18 17:32:41 +00:00
|
|
|
fn allocate_bars(
|
|
|
|
&mut self,
|
|
|
|
allocator: &mut SystemAllocator,
|
2019-07-19 17:50:30 +00:00
|
|
|
) -> std::result::Result<Vec<(GuestAddress, GuestUsize, PciBarRegionType)>, PciDeviceError>
|
|
|
|
{
|
2019-04-18 17:32:41 +00:00
|
|
|
let mut ranges = Vec::new();
|
2019-11-18 23:10:42 +00:00
|
|
|
let device_clone = self.device.clone();
|
|
|
|
let device = device_clone.lock().unwrap();
|
2019-04-18 17:32:41 +00:00
|
|
|
|
|
|
|
// Allocate the virtio-pci capability BAR.
|
|
|
|
// See http://docs.oasis-open.org/virtio/virtio/v1.0/cs04/virtio-v1.0-cs04.html#x1-740004
|
2019-09-20 21:48:34 +00:00
|
|
|
let (virtio_pci_bar_addr, region_type) = if self.use_64bit_bar {
|
|
|
|
let region_type = PciBarRegionType::Memory64BitRegion;
|
2019-09-17 16:34:51 +00:00
|
|
|
let addr = allocator
|
|
|
|
.allocate_mmio_addresses(None, CAPABILITY_BAR_SIZE, None)
|
|
|
|
.ok_or(PciDeviceError::IoAllocationFailed(CAPABILITY_BAR_SIZE))?;
|
2019-09-20 21:48:34 +00:00
|
|
|
ranges.push((addr, CAPABILITY_BAR_SIZE, region_type));
|
|
|
|
(addr, region_type)
|
2019-09-17 16:34:51 +00:00
|
|
|
} else {
|
2019-09-20 21:48:34 +00:00
|
|
|
let region_type = PciBarRegionType::Memory32BitRegion;
|
2019-09-17 16:34:51 +00:00
|
|
|
let addr = allocator
|
|
|
|
.allocate_mmio_hole_addresses(None, CAPABILITY_BAR_SIZE, None)
|
|
|
|
.ok_or(PciDeviceError::IoAllocationFailed(CAPABILITY_BAR_SIZE))?;
|
2019-09-20 21:48:34 +00:00
|
|
|
ranges.push((addr, CAPABILITY_BAR_SIZE, region_type));
|
|
|
|
(addr, region_type)
|
2019-09-17 16:34:51 +00:00
|
|
|
};
|
|
|
|
|
2019-04-18 17:32:41 +00:00
|
|
|
let config = PciBarConfiguration::default()
|
|
|
|
.set_register_index(0)
|
|
|
|
.set_address(virtio_pci_bar_addr.raw_value())
|
2019-09-20 21:48:34 +00:00
|
|
|
.set_size(CAPABILITY_BAR_SIZE)
|
|
|
|
.set_region_type(region_type);
|
2019-04-18 17:32:41 +00:00
|
|
|
let virtio_pci_bar =
|
|
|
|
self.configuration.add_pci_bar(&config).map_err(|e| {
|
|
|
|
PciDeviceError::IoRegistrationFailed(virtio_pci_bar_addr.raw_value(), e)
|
|
|
|
})? as u8;
|
|
|
|
|
|
|
|
// Once the BARs are allocated, the capabilities can be added to the PCI configuration.
|
|
|
|
self.add_pci_capabilities(virtio_pci_bar)?;
|
|
|
|
|
2019-08-06 00:58:55 +00:00
|
|
|
// Allocate a dedicated BAR if there are some shared memory regions.
|
2019-11-18 23:10:42 +00:00
|
|
|
if let Some(shm_list) = device.get_shm_regions() {
|
2019-08-06 00:58:55 +00:00
|
|
|
let config = PciBarConfiguration::default()
|
|
|
|
.set_register_index(2)
|
|
|
|
.set_address(shm_list.addr.raw_value())
|
|
|
|
.set_size(shm_list.len);
|
|
|
|
let virtio_pci_shm_bar =
|
|
|
|
self.configuration.add_pci_bar(&config).map_err(|e| {
|
|
|
|
PciDeviceError::IoRegistrationFailed(shm_list.addr.raw_value(), e)
|
|
|
|
})? as u8;
|
|
|
|
|
|
|
|
for (idx, shm) in shm_list.region_list.iter().enumerate() {
|
|
|
|
let shm_cap = VirtioPciCap64::new(
|
|
|
|
PciCapabilityType::SharedMemoryConfig,
|
|
|
|
virtio_pci_shm_bar,
|
|
|
|
idx as u8,
|
|
|
|
shm.offset,
|
|
|
|
shm.len,
|
|
|
|
);
|
|
|
|
self.configuration
|
|
|
|
.add_capability(&shm_cap)
|
|
|
|
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-04-18 17:32:41 +00:00
|
|
|
Ok(ranges)
|
|
|
|
}
|
|
|
|
|
2019-07-02 23:27:38 +00:00
|
|
|
fn read_bar(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
|
2019-04-18 17:32:41 +00:00
|
|
|
match offset {
|
|
|
|
o if o < COMMON_CONFIG_BAR_OFFSET + COMMON_CONFIG_SIZE => self.common_config.read(
|
|
|
|
o - COMMON_CONFIG_BAR_OFFSET,
|
|
|
|
data,
|
|
|
|
&mut self.queues,
|
2019-11-18 23:10:42 +00:00
|
|
|
self.device.clone(),
|
2019-04-18 17:32:41 +00:00
|
|
|
),
|
|
|
|
o if ISR_CONFIG_BAR_OFFSET <= o && o < ISR_CONFIG_BAR_OFFSET + ISR_CONFIG_SIZE => {
|
|
|
|
if let Some(v) = data.get_mut(0) {
|
|
|
|
// Reading this register resets it to 0.
|
|
|
|
*v = self.interrupt_status.swap(0, Ordering::SeqCst) as u8;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
o if DEVICE_CONFIG_BAR_OFFSET <= o
|
|
|
|
&& o < DEVICE_CONFIG_BAR_OFFSET + DEVICE_CONFIG_SIZE =>
|
|
|
|
{
|
2019-11-18 23:10:42 +00:00
|
|
|
let device = self.device.lock().unwrap();
|
|
|
|
device.read_config(o - DEVICE_CONFIG_BAR_OFFSET, data);
|
2019-04-18 17:32:41 +00:00
|
|
|
}
|
|
|
|
o if NOTIFICATION_BAR_OFFSET <= o
|
|
|
|
&& o < NOTIFICATION_BAR_OFFSET + NOTIFICATION_SIZE =>
|
|
|
|
{
|
|
|
|
// Handled with ioeventfds.
|
|
|
|
}
|
2019-05-29 23:33:29 +00:00
|
|
|
o if MSIX_TABLE_BAR_OFFSET <= o && o < MSIX_TABLE_BAR_OFFSET + MSIX_TABLE_SIZE => {
|
2019-06-07 16:19:46 +00:00
|
|
|
if let Some(msix_config) = &self.msix_config {
|
|
|
|
msix_config
|
|
|
|
.lock()
|
|
|
|
.unwrap()
|
|
|
|
.read_table(o - MSIX_TABLE_BAR_OFFSET, data);
|
|
|
|
}
|
2019-05-29 23:33:29 +00:00
|
|
|
}
|
|
|
|
o if MSIX_PBA_BAR_OFFSET <= o && o < MSIX_PBA_BAR_OFFSET + MSIX_PBA_SIZE => {
|
2019-06-07 16:19:46 +00:00
|
|
|
if let Some(msix_config) = &self.msix_config {
|
|
|
|
msix_config
|
|
|
|
.lock()
|
|
|
|
.unwrap()
|
|
|
|
.read_pba(o - MSIX_PBA_BAR_OFFSET, data);
|
|
|
|
}
|
2019-05-29 23:33:29 +00:00
|
|
|
}
|
2019-04-18 17:32:41 +00:00
|
|
|
_ => (),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-02 23:27:38 +00:00
|
|
|
fn write_bar(&mut self, _base: u64, offset: u64, data: &[u8]) {
|
2019-04-18 17:32:41 +00:00
|
|
|
match offset {
|
|
|
|
o if o < COMMON_CONFIG_BAR_OFFSET + COMMON_CONFIG_SIZE => self.common_config.write(
|
|
|
|
o - COMMON_CONFIG_BAR_OFFSET,
|
|
|
|
data,
|
|
|
|
&mut self.queues,
|
2019-11-18 23:10:42 +00:00
|
|
|
self.device.clone(),
|
2019-04-18 17:32:41 +00:00
|
|
|
),
|
|
|
|
o if ISR_CONFIG_BAR_OFFSET <= o && o < ISR_CONFIG_BAR_OFFSET + ISR_CONFIG_SIZE => {
|
|
|
|
if let Some(v) = data.get(0) {
|
|
|
|
self.interrupt_status
|
|
|
|
.fetch_and(!(*v as usize), Ordering::SeqCst);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
o if DEVICE_CONFIG_BAR_OFFSET <= o
|
|
|
|
&& o < DEVICE_CONFIG_BAR_OFFSET + DEVICE_CONFIG_SIZE =>
|
|
|
|
{
|
2019-11-18 23:10:42 +00:00
|
|
|
let mut device = self.device.lock().unwrap();
|
|
|
|
device.write_config(o - DEVICE_CONFIG_BAR_OFFSET, data);
|
2019-04-18 17:32:41 +00:00
|
|
|
}
|
|
|
|
o if NOTIFICATION_BAR_OFFSET <= o
|
|
|
|
&& o < NOTIFICATION_BAR_OFFSET + NOTIFICATION_SIZE =>
|
|
|
|
{
|
|
|
|
// Handled with ioeventfds.
|
|
|
|
}
|
2019-05-29 23:33:29 +00:00
|
|
|
o if MSIX_TABLE_BAR_OFFSET <= o && o < MSIX_TABLE_BAR_OFFSET + MSIX_TABLE_SIZE => {
|
2019-06-07 16:19:46 +00:00
|
|
|
if let Some(msix_config) = &self.msix_config {
|
|
|
|
msix_config
|
|
|
|
.lock()
|
|
|
|
.unwrap()
|
|
|
|
.write_table(o - MSIX_TABLE_BAR_OFFSET, data);
|
|
|
|
}
|
2019-05-29 23:33:29 +00:00
|
|
|
}
|
|
|
|
o if MSIX_PBA_BAR_OFFSET <= o && o < MSIX_PBA_BAR_OFFSET + MSIX_PBA_SIZE => {
|
2019-06-07 16:19:46 +00:00
|
|
|
if let Some(msix_config) = &self.msix_config {
|
|
|
|
msix_config
|
|
|
|
.lock()
|
|
|
|
.unwrap()
|
|
|
|
.write_pba(o - MSIX_PBA_BAR_OFFSET, data);
|
|
|
|
}
|
2019-05-29 23:33:29 +00:00
|
|
|
}
|
2019-04-18 17:32:41 +00:00
|
|
|
_ => (),
|
|
|
|
};
|
|
|
|
|
|
|
|
if !self.device_activated && self.is_driver_ready() && self.are_queues_valid() {
|
2019-06-03 20:57:26 +00:00
|
|
|
if let Some(interrupt_cb) = self.interrupt_cb.take() {
|
2019-05-08 14:59:39 +00:00
|
|
|
if self.memory.is_some() {
|
|
|
|
let mem = self.memory.as_ref().unwrap().clone();
|
2019-11-18 23:10:42 +00:00
|
|
|
let mut device = self.device.lock().unwrap();
|
|
|
|
device
|
2019-04-18 17:32:41 +00:00
|
|
|
.activate(
|
|
|
|
mem,
|
2019-06-03 20:57:26 +00:00
|
|
|
interrupt_cb,
|
2019-04-18 17:32:41 +00:00
|
|
|
self.queues.clone(),
|
|
|
|
self.queue_evts.split_off(0),
|
|
|
|
)
|
2019-06-03 20:57:26 +00:00
|
|
|
.expect("Failed to activate device");
|
2019-04-18 17:32:41 +00:00
|
|
|
self.device_activated = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2019-05-08 14:59:39 +00:00
|
|
|
|
|
|
|
// Device has been reset by the driver
|
|
|
|
if self.device_activated && self.is_driver_init() {
|
2019-11-18 23:10:42 +00:00
|
|
|
let mut device = self.device.lock().unwrap();
|
|
|
|
if let Some((interrupt_cb, mut queue_evts)) = device.reset() {
|
2019-05-08 14:59:39 +00:00
|
|
|
// Upon reset the device returns its interrupt EventFD and it's queue EventFDs
|
2019-06-03 20:57:26 +00:00
|
|
|
self.interrupt_cb = Some(interrupt_cb);
|
2019-05-08 14:59:39 +00:00
|
|
|
self.queue_evts.append(&mut queue_evts);
|
|
|
|
|
|
|
|
self.device_activated = false;
|
|
|
|
|
|
|
|
// Reset queue readiness (changes queue_enable), queue sizes
|
|
|
|
// and selected_queue as per spec for reset
|
|
|
|
self.queues.iter_mut().for_each(Queue::reset);
|
|
|
|
self.common_config.queue_select = 0;
|
|
|
|
} else {
|
|
|
|
error!("Attempt to reset device when not implemented in underlying device");
|
|
|
|
self.common_config.driver_status = crate::DEVICE_FAILED as u8;
|
|
|
|
}
|
|
|
|
}
|
2019-04-18 17:32:41 +00:00
|
|
|
}
|
2019-10-30 15:15:38 +00:00
|
|
|
|
|
|
|
fn as_any(&mut self) -> &mut dyn Any {
|
|
|
|
self
|
|
|
|
}
|
2019-04-18 17:32:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
impl BusDevice for VirtioPciDevice {
|
2019-07-02 23:27:38 +00:00
|
|
|
fn read(&mut self, base: u64, offset: u64, data: &mut [u8]) {
|
|
|
|
self.read_bar(base, offset, data)
|
2019-04-18 17:32:41 +00:00
|
|
|
}
|
|
|
|
|
2019-07-02 23:27:38 +00:00
|
|
|
fn write(&mut self, base: u64, offset: u64, data: &[u8]) {
|
|
|
|
self.write_bar(base, offset, data)
|
2019-04-18 17:32:41 +00:00
|
|
|
}
|
|
|
|
}
|
2019-11-19 00:42:31 +00:00
|
|
|
|
|
|
|
impl Pausable for VirtioPciDevice {
|
|
|
|
fn pause(&mut self) -> result::Result<(), MigratableError> {
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
|
|
|
|
fn resume(&mut self) -> result::Result<(), MigratableError> {
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl Snapshotable for VirtioPciDevice {}
|
|
|
|
impl Migratable for VirtioPciDevice {}
|