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devices: legacy: Fix beta clippy issues

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error: unneeded late initalization
Error:    --> devices/src/legacy/rtc_pl031.rs:294:9
    |
294 |         let v;
    |         ^^^^^^
    |
    = note: `-D clippy::needless-late-init` implied by `-D warnings`
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#needless_late_init
help: declare `v` here
    |
297 |         let v = if (AMBA_ID_LOW..AMBA_ID_HIGH).contains(&offset) {
    |         +++++++
help: remove the assignments from the branches
    |
299 ~             u32::from(PL031_ID[index])
300 |         } else {
301 ~             match offset {
302 |                 RTCDR => self.get_time(),
303 |                 RTCMR => {
304 |                     // Even though we are not implementing RTC alarm we return the last value
  ...
help: add a semicolon after the `if` expression
    |
317 |         };
    |          +

error: unneeded late initalization
Error:    --> devices/src/legacy/uart_pl011.rs:297:9
    |
297 |         let v;
    |         ^^^^^^
    |
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#needless_late_init
help: declare `v` here
    |
299 |         let v = if (AMBA_ID_LOW..AMBA_ID_HIGH).contains(&(offset >> 2)) {
    |         +++++++
help: remove the assignments from the branches
    |
301 ~             u32::from(PL011_ID[index])
302 |         } else {
303 ~             match offset >> 2 {
304 |                 UARTDR => {
305 |                     let c: u32;
306 |                     let r: u32;
  ...
help: add a semicolon after the `if` expression
    |
340 |         };
    |          +

error: unneeded late initalization
Error:    --> devices/src/legacy/uart_pl011.rs:305:21
    |
305 |                     let c: u32;
    |                     ^^^^^^^^^^^
    |
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#needless_late_init
help: declare `c` here
    |
309 |                     let c: u32 = self.read_fifo.pop_front().unwrap_or_default().into();
    |                     ~~~~~~~~~~

error: unneeded late initalization
Error:    --> devices/src/legacy/uart_pl011.rs:306:21
    |
306 |                     let r: u32;
    |                     ^^^^^^^^^^^
    |
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#needless_late_init
help: declare `r` here
    |
320 |                     let r: u32 = c;
    |                     ~~~~~~~~~~

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford 2022-01-14 13:51:29 +00:00
parent 0a97b76c52
commit 1dc913427c
2 changed files with 11 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
devices/src/legacy/rtc_pl031.rs
View File

@ -291,14 +291,13 @@ impl Rtc {
impl BusDevice for Rtc {
fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
let v;
let mut read_ok = true;
if (AMBA_ID_LOW..AMBA_ID_HIGH).contains(&offset) {
let v = if (AMBA_ID_LOW..AMBA_ID_HIGH).contains(&offset) {
let index = ((offset - AMBA_ID_LOW) >> 2) as usize;
v = u32::from(PL031_ID[index]);
u32::from(PL031_ID[index])
} else {
v = match offset {
match offset {
RTCDR => self.get_time(),
RTCMR => {
// Even though we are not implementing RTC alarm we return the last value
@ -313,8 +312,8 @@ impl BusDevice for Rtc {
read_ok = false;
0
}
};
}
}
};
if read_ok && data.len() <= 4 {
write_le_u32(data, v);
} else {

17
devices/src/legacy/uart_pl011.rs
View File

@ -294,19 +294,15 @@ impl Pl011 {
impl BusDevice for Pl011 {
fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
let v;
let mut read_ok = true;
if (AMBA_ID_LOW..AMBA_ID_HIGH).contains(&(offset >> 2)) {
let v = if (AMBA_ID_LOW..AMBA_ID_HIGH).contains(&(offset >> 2)) {
let index = ((offset - 0xfe0) >> 2) as usize;
v = u32::from(PL011_ID[index]);
u32::from(PL011_ID[index])
} else {
v = match offset >> 2 {
match offset >> 2 {
UARTDR => {
let c: u32;
let r: u32;
self.flags &= !PL011_FLAG_RXFF;
c = self.read_fifo.pop_front().unwrap_or_default().into();
let c: u32 = self.read_fifo.pop_front().unwrap_or_default().into();
if self.read_count > 0 {
self.read_count -= 1;
}
@ -317,8 +313,7 @@ impl BusDevice for Pl011 {
self.int_level &= !PL011_INT_RX;
}
self.rsr = c >> 8;
r = c;
r
c
}
UARTRSR_UARTECR => self.rsr,
UARTFR => self.flags,
@ -337,7 +332,7 @@ impl BusDevice for Pl011 {
0
}
}
}
};
if read_ok && data.len() <= 4 {
write_le_u32(data, v);