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hypervisor: mshv: Restrict APIC EOI message to x86

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APIC controller is only available on x86 machine. ARM uses a different
interrupt controller so those exit messages won't happen for ARM guests.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
This commit is contained in:
Jinank Jain 2024-03-21 09:31:05 +05:30 committed by Rob Bradford
parent dad1ab1227
commit 2501426e47
1 changed files with 1 additions and 0 deletions
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hypervisor/src/mshv/mod.rs
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@ -706,6 +706,7 @@ impl cpu::Vcpu for MshvVcpu {
debug!("Exception Info {:?}", { info.exception_vector }); debug!("Exception Info {:?}", { info.exception_vector });
Ok(cpu::VmExit::Ignore) Ok(cpu::VmExit::Ignore)
} }
#[cfg(target_arch = "x86_64")]
hv_message_type_HVMSG_X64_APIC_EOI => { hv_message_type_HVMSG_X64_APIC_EOI => {
let info = x.to_apic_eoi_info().unwrap(); let info = x.to_apic_eoi_info().unwrap();
// The kernel should dispatch the EOI to the correct thread. // The kernel should dispatch the EOI to the correct thread.