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pci: Implement the From trait for the PciCapabilityID structure

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This will be needed by the VFIO crate for managing MSI capabilities.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Samuel Ortiz 2019-07-03 19:15:50 +02:00 committed by Sebastien Boeuf
parent 3f02ccaa8c
commit 29878956bd
1 changed files with 33 additions and 1 deletions
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34
pci/src/configuration.rs
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@ -178,7 +178,10 @@ pub trait PciProgrammingInterface {
}
/// Types of PCI capabilities.
#[derive(PartialEq)]
#[derive(PartialEq, Copy, Clone)]
#[allow(dead_code)]
#[allow(non_camel_case_types)]
#[repr(C)]
pub enum PciCapabilityID {
ListID = 0,
PowerManagement = 0x01,
@ -203,6 +206,35 @@ pub enum PciCapabilityID {
PCIEnhancedAllocation = 0x14,
}
impl From<u8> for PciCapabilityID {
fn from(c: u8) -> Self {
match c {
0 => PciCapabilityID::ListID,
0x01 => PciCapabilityID::PowerManagement,
0x02 => PciCapabilityID::AcceleratedGraphicsPort,
0x03 => PciCapabilityID::VitalProductData,
0x04 => PciCapabilityID::SlotIdentification,
0x05 => PciCapabilityID::MessageSignalledInterrupts,
0x06 => PciCapabilityID::CompactPCIHotSwap,
0x07 => PciCapabilityID::PCIX,
0x08 => PciCapabilityID::HyperTransport,
0x09 => PciCapabilityID::VendorSpecific,
0x0A => PciCapabilityID::Debugport,
0x0B => PciCapabilityID::CompactPCICentralResourceControl,
0x0C => PciCapabilityID::PCIStandardHotPlugController,
0x0D => PciCapabilityID::BridgeSubsystemVendorDeviceID,
0x0E => PciCapabilityID::AGPTargetPCIPCIbridge,
0x0F => PciCapabilityID::SecureDevice,
0x10 => PciCapabilityID::PCIExpress,
0x11 => PciCapabilityID::MSIX,
0x12 => PciCapabilityID::SATADataIndexConf,
0x13 => PciCapabilityID::PCIAdvancedFeatures,
0x14 => PciCapabilityID::PCIEnhancedAllocation,
_ => PciCapabilityID::ListID,
}
}
}
/// A PCI capability list. Devices can optionally specify capabilities in their configuration space.
pub trait PciCapability {
fn bytes(&self) -> &[u8];