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pci: Implement the From trait for the PciCapabilityID structure
This will be needed by the VFIO crate for managing MSI capabilities. Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
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@ -178,7 +178,10 @@ pub trait PciProgrammingInterface {
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}
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}
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/// Types of PCI capabilities.
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/// Types of PCI capabilities.
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#[derive(PartialEq)]
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#[derive(PartialEq, Copy, Clone)]
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#[allow(dead_code)]
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#[allow(non_camel_case_types)]
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#[repr(C)]
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pub enum PciCapabilityID {
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pub enum PciCapabilityID {
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ListID = 0,
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ListID = 0,
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PowerManagement = 0x01,
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PowerManagement = 0x01,
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@ -203,6 +206,35 @@ pub enum PciCapabilityID {
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PCIEnhancedAllocation = 0x14,
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PCIEnhancedAllocation = 0x14,
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}
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}
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impl From<u8> for PciCapabilityID {
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fn from(c: u8) -> Self {
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match c {
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0 => PciCapabilityID::ListID,
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0x01 => PciCapabilityID::PowerManagement,
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0x02 => PciCapabilityID::AcceleratedGraphicsPort,
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0x03 => PciCapabilityID::VitalProductData,
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0x04 => PciCapabilityID::SlotIdentification,
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0x05 => PciCapabilityID::MessageSignalledInterrupts,
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0x06 => PciCapabilityID::CompactPCIHotSwap,
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0x07 => PciCapabilityID::PCIX,
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0x08 => PciCapabilityID::HyperTransport,
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0x09 => PciCapabilityID::VendorSpecific,
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0x0A => PciCapabilityID::Debugport,
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0x0B => PciCapabilityID::CompactPCICentralResourceControl,
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0x0C => PciCapabilityID::PCIStandardHotPlugController,
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0x0D => PciCapabilityID::BridgeSubsystemVendorDeviceID,
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0x0E => PciCapabilityID::AGPTargetPCIPCIbridge,
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0x0F => PciCapabilityID::SecureDevice,
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0x10 => PciCapabilityID::PCIExpress,
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0x11 => PciCapabilityID::MSIX,
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0x12 => PciCapabilityID::SATADataIndexConf,
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0x13 => PciCapabilityID::PCIAdvancedFeatures,
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0x14 => PciCapabilityID::PCIEnhancedAllocation,
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_ => PciCapabilityID::ListID,
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}
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}
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}
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/// A PCI capability list. Devices can optionally specify capabilities in their configuration space.
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/// A PCI capability list. Devices can optionally specify capabilities in their configuration space.
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pub trait PciCapability {
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pub trait PciCapability {
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fn bytes(&self) -> &[u8];
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fn bytes(&self) -> &[u8];
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