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hypervisor: Refactor system_registers
on AArch64
Function `system_registers` took mutable vector reference and modified the vector content. Now change the definition to `get/set` style. And rename to `get/set_sys_regs` to align with other functions. Signed-off-by: Michael Zhao <michael.zhao@arm.com>
This commit is contained in:
parent
c445513976
commit
2d8635f04a
@ -429,12 +429,12 @@ pub trait Vcpu: Send + Sync {
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/// Save the state of the system registers.
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/// Save the state of the system registers.
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///
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///
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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fn system_registers(&self, state: &mut Vec<Register>) -> Result<()>;
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fn get_sys_regs(&self) -> Result<Vec<Register>>;
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///
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///
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/// Restore the state of the system registers.
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/// Restore the state of the system registers.
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///
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///
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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fn set_system_registers(&self, state: &[Register]) -> Result<()>;
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fn set_sys_regs(&self, state: &[Register]) -> Result<()>;
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///
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///
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/// Read the MPIDR - Multiprocessor Affinity Register.
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/// Read the MPIDR - Multiprocessor Affinity Register.
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///
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///
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@ -1573,9 +1573,10 @@ impl cpu::Vcpu for KvmVcpu {
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/// Save the state of the system registers.
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/// Save the state of the system registers.
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///
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///
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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fn system_registers(&self, state: &mut Vec<Register>) -> cpu::Result<()> {
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fn get_sys_regs(&self) -> cpu::Result<Vec<Register>> {
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// Call KVM_GET_REG_LIST to get all registers available to the guest. For ArmV8 there are
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// Call KVM_GET_REG_LIST to get all registers available to the guest. For ArmV8 there are
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// around 500 registers.
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// around 500 registers.
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let mut state: Vec<Register> = Vec::new();
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let mut reg_list = RegList::new(500).unwrap();
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let mut reg_list = RegList::new(500).unwrap();
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self.fd
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self.fd
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.get_reg_list(&mut reg_list)
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.get_reg_list(&mut reg_list)
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@ -1601,13 +1602,13 @@ impl cpu::Vcpu for KvmVcpu {
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});
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});
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}
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}
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Ok(())
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Ok(state)
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}
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}
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///
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///
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/// Restore the state of the system registers.
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/// Restore the state of the system registers.
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///
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///
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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fn set_system_registers(&self, state: &[Register]) -> cpu::Result<()> {
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fn set_sys_regs(&self, state: &[Register]) -> cpu::Result<()> {
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for reg in state {
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for reg in state {
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self.fd
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self.fd
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.set_one_reg(reg.id, reg.addr)
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.set_one_reg(reg.id, reg.addr)
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@ -1811,7 +1812,7 @@ impl cpu::Vcpu for KvmVcpu {
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..Default::default()
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..Default::default()
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};
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};
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state.core_regs = self.get_regs()?;
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state.core_regs = self.get_regs()?;
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self.system_registers(&mut state.sys_regs)?;
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state.sys_regs = self.get_sys_regs()?;
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Ok(state)
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Ok(state)
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}
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}
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@ -1905,7 +1906,7 @@ impl cpu::Vcpu for KvmVcpu {
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#[cfg(target_arch = "aarch64")]
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#[cfg(target_arch = "aarch64")]
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fn set_state(&self, state: &CpuState) -> cpu::Result<()> {
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fn set_state(&self, state: &CpuState) -> cpu::Result<()> {
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self.set_regs(&state.core_regs)?;
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self.set_regs(&state.core_regs)?;
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self.set_system_registers(&state.sys_regs)?;
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self.set_sys_regs(&state.sys_regs)?;
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self.set_mp_state(state.mp_state)?;
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self.set_mp_state(state.mp_state)?;
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Ok(())
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Ok(())
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@ -2537,10 +2537,10 @@ mod tests {
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// Must fail when vcpu is not initialized yet.
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// Must fail when vcpu is not initialized yet.
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let mut state: Vec<kvm_one_reg> = Vec::new();
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let mut state: Vec<kvm_one_reg> = Vec::new();
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let res = vcpu.system_registers(&mut state);
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let res = vcpu.get_sys_regs();
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assert!(res.is_err());
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assert!(res.is_err());
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assert_eq!(
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assert_eq!(
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format!("{}", res.unwrap_err()),
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format!("{}", res.as_ref().unwrap_err()),
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"Failed to retrieve list of registers: Exec format error (os error 8)"
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"Failed to retrieve list of registers: Exec format error (os error 8)"
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);
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);
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@ -2548,7 +2548,7 @@ mod tests {
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id: MPIDR_EL1,
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id: MPIDR_EL1,
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addr: 0x00,
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addr: 0x00,
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});
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});
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let res = vcpu.set_system_registers(&state);
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let res = vcpu.set_sys_regs(&state);
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assert!(res.is_err());
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assert!(res.is_err());
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assert_eq!(
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assert_eq!(
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format!("{}", res.unwrap_err()),
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format!("{}", res.unwrap_err()),
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@ -2556,14 +2556,17 @@ mod tests {
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);
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);
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vcpu.vcpu_init(&kvi).unwrap();
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vcpu.vcpu_init(&kvi).unwrap();
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assert!(vcpu.system_registers(&mut state).is_ok());
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let res = vcpu.get_sys_regs();
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assert!(res.is_ok());
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state = res.unwrap();
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let initial_mpidr: u64 = vcpu.read_mpidr().expect("Fail to read mpidr");
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let initial_mpidr: u64 = vcpu.read_mpidr().expect("Fail to read mpidr");
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assert!(state.contains(&kvm_one_reg {
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assert!(state.contains(&kvm_one_reg {
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id: MPIDR_EL1,
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id: MPIDR_EL1,
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addr: initial_mpidr
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addr: initial_mpidr
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}));
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}));
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assert!(vcpu.set_system_registers(&state).is_ok());
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assert!(vcpu.set_sys_regs(&state).is_ok());
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let mpidr: u64 = vcpu.read_mpidr().expect("Fail to read mpidr");
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let mpidr: u64 = vcpu.read_mpidr().expect("Fail to read mpidr");
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assert_eq!(initial_mpidr, mpidr);
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assert_eq!(initial_mpidr, mpidr);
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}
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}
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