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hypervisor: Set MTRRdefType in MSHV guest initialization to enable cpu caching

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Initialize MTRR defType register the same way the KVM code does - WB caching by default.
Tested with latest mshv code.

Without this patch, these lines are present in guest serial log:
[ 0.000032] x86/PAT: MTRRs disabled, skipping PAT initialization too.
[ 0.000036] CPU MTRRs all blank - virtualized system.
This indicates the guest is detecting the set MTRR.

Signed-off-by: Nuno Das Neves <nudasnev@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>
This commit is contained in:
Muminul Islam 2021-06-22 11:35:02 -07:00 committed by Rob Bradford
parent 4d25eaa24a
commit 5432cbfaad
1 changed files with 2 additions and 1 deletions
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3
hypervisor/src/mshv/x86_64/mod.rs
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@ -8,7 +8,7 @@
//
//
use crate::arch::x86::{msr_index, SegmentRegisterOps};
use crate::arch::x86::{msr_index, SegmentRegisterOps, MTRR_ENABLE, MTRR_MEM_TYPE_WB};
use serde_derive::{Deserialize, Serialize};
///
/// Export generically-named wrappers of mshv_bindings for Unix-based platforms
@ -118,6 +118,7 @@ pub fn boot_msr_entries() -> MsrEntries {
msr!(msr_index::MSR_KERNEL_GS_BASE),
msr!(msr_index::MSR_SYSCALL_MASK),
msr!(msr_index::MSR_IA32_TSC),
msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB),
])
.unwrap()
}