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https://github.com/cloud-hypervisor/cloud-hypervisor.git
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Revert "vmm: Move CpuManager device to MMIO region"
This reverts commit 980e03fa0a.
This commit is contained in:
Rob Bradford
Sebastien Boeuf
parent
6475052692
commit
6120d0fb1b
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@ -114,8 +114,8 @@ pub enum Error {
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/// Cannot add legacy device to Bus.
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BusError(devices::BusError),
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/// Failed to allocate MMIO range
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AllocateMMIO,
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/// Failed to allocate IO port
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AllocateIOPort,
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/// Asking for more vCPUs that we can have
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DesiredVCPUCountExceedsMax,
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@ -373,8 +373,8 @@ impl Vcpu {
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pub struct CpuManager {
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boot_vcpus: u8,
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max_vcpus: u8,
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io_bus: Arc<devices::Bus>,
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mmio_bus: Weak<devices::Bus>,
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io_bus: Weak<devices::Bus>,
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mmio_bus: Arc<devices::Bus>,
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ioapic: Option<Arc<Mutex<ioapic::Ioapic>>>,
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vm_memory: Arc<ArcSwap<GuestMemoryMmap>>,
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cpuid: CpuId,
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@ -384,8 +384,6 @@ pub struct CpuManager {
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reset_evt: EventFd,
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vcpu_states: Vec<VcpuState>,
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selected_cpu: u8,
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#[cfg(feature = "acpi")]
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device_base: GuestAddress,
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}
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const CPU_ENABLE_FLAG: usize = 0;
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@ -494,8 +492,6 @@ impl VcpuState {
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}
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impl CpuManager {
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pub const DEVICE_SIZE: u64 = 0xc;
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pub fn new(
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boot_vcpus: u8,
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max_vcpus: u8,
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@ -508,19 +504,11 @@ impl CpuManager {
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let mut vcpu_states = Vec::with_capacity(usize::from(max_vcpus));
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vcpu_states.resize_with(usize::from(max_vcpus), VcpuState::default);
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#[cfg(feature = "acpi")]
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let device_base = device_manager
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.allocator()
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.lock()
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.unwrap()
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.allocate_mmio_addresses(None, CpuManager::DEVICE_SIZE, None)
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.ok_or(Error::AllocateMMIO)?;
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let cpu_manager = Arc::new(Mutex::new(CpuManager {
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boot_vcpus,
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max_vcpus,
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io_bus: device_manager.io_bus().clone(),
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mmio_bus: Arc::downgrade(&device_manager.mmio_bus().clone()),
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io_bus: Arc::downgrade(&device_manager.io_bus().clone()),
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mmio_bus: device_manager.mmio_bus().clone(),
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ioapic: device_manager.ioapic().clone(),
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vm_memory: guest_memory,
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cpuid,
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@ -530,18 +518,22 @@ impl CpuManager {
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vcpu_states,
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reset_evt,
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selected_cpu: 0,
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#[cfg(feature = "acpi")]
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device_base,
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}));
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#[cfg(feature = "acpi")]
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device_manager
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.allocator()
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.lock()
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.unwrap()
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.allocate_io_addresses(Some(GuestAddress(0x0cd8)), 0x8, None)
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.ok_or(Error::AllocateIOPort)?;
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cpu_manager
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.lock()
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.unwrap()
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.mmio_bus
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.io_bus
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.upgrade()
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.unwrap()
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.insert(cpu_manager.clone(), device_base.0, CpuManager::DEVICE_SIZE)
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.insert(cpu_manager.clone(), 0x0cd8, 0xc)
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.map_err(Error::BusError)?;
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Ok(cpu_manager)
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@ -571,8 +563,8 @@ impl CpuManager {
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let mut vcpu = Vcpu::new(
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cpu_id,
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&self.fd,
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self.io_bus.clone(),
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self.mmio_bus.clone().upgrade().unwrap(),
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self.io_bus.clone().upgrade().unwrap(),
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self.mmio_bus.clone(),
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ioapic,
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creation_ts,
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)?;
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@ -860,7 +852,7 @@ impl Aml for CPUMethods {
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vec![
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// Take lock defined above
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&aml::Acquire::new("\\_SB_.PRES.CPLK".into(), 0xfff),
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// Write CPU number (in first argument) to MMIO region via field
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// Write CPU number (in first argument) to I/O port via field
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CSEL"), &aml::Arg(0)),
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&aml::Store::new(&aml::Local(0), &aml::ZERO),
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// Check if CPEN bit is set, if so make the local variable 0xf (see _STA for details of meaning)
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@ -898,7 +890,7 @@ impl Aml for CPUMethods {
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true,
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vec![
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&aml::Acquire::new("\\_SB_.PRES.CPLK".into(), 0xfff),
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// Write CPU number (in first argument) to MMIO region via field
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// Write CPU number (in first argument) to I/O port via field
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CSEL"), &aml::Arg(0)),
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// Set CEJ0 bit
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CEJ0"), &aml::ONE),
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@ -920,7 +912,7 @@ impl Aml for CPUMethods {
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&aml::While::new(
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&aml::LessThan::new(&aml::Local(0), &self.max_vcpus),
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vec![
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// Write CPU number (in first argument) to MMIO region via field
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// Write CPU number (in first argument) to I/O port via field
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CSEL"), &aml::Local(0)),
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// Check if CINS bit is set
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&aml::If::new(
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@ -979,23 +971,15 @@ impl Aml for CpuManager {
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&aml::Name::new("_HID".into(), &aml::EISAName::new("PNP0A06")),
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// Mutex to protect concurrent access as we write to choose CPU and then read back status
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&aml::Mutex::new("CPLK".into(), 0),
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// MMIO region for CPU controller
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// I/O port for CPU controller
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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self.device_base.0,
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self.device_base.0 + CpuManager::DEVICE_SIZE - 1,
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&aml::ResourceTemplate::new(vec![&aml::IO::new(
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0x0cd8, 0x0cd8, 0x01, 0x0c,
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)]),
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),
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// OpRegion and Fields map MMIO region into individual field values
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&aml::OpRegion::new(
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"PRST".into(),
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aml::OpRegionSpace::SystemMemory,
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self.device_base.0 as usize,
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CpuManager::DEVICE_SIZE as usize,
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),
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// OpRegion and Fields map I/O port into individual field values
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&aml::OpRegion::new("PRST".into(), aml::OpRegionSpace::SystemIO, 0x0cd8, 0x0c),
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&aml::Field::new(
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"PRST".into(),
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aml::FieldAccessType::Byte,
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