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vmm: Only fill in PIO and 32-bit MMIO space on zero segment
Since each segment must have disjoint address spaces only advertise address space in the 32-bit range and the PIO address space on the default (zero) segment. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
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3059ba4305
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@ -356,35 +356,56 @@ impl Aml for PciSegment {
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let pci_dsm = PciDsmMethod {};
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pci_dsdt_inner_data.push(&pci_dsm);
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let crs = aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![
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&aml::AddressSpace::new_bus_number(0x0u16, 0x0u16),
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#[cfg(target_arch = "x86_64")]
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&aml::Io::new(0xcf8, 0xcf8, 1, 0x8),
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&aml::Memory32Fixed::new(
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true,
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self.mmio_config_address as u32,
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PCI_MMIO_CONFIG_SIZE as u32,
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),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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layout::MEM_32BIT_DEVICES_START.0 as u32,
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(layout::MEM_32BIT_DEVICES_START.0 + layout::MEM_32BIT_DEVICES_SIZE - 1) as u32,
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),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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self.start_of_device_area,
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self.end_of_device_area,
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),
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#[cfg(target_arch = "x86_64")]
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&aml::AddressSpace::new_io(0u16, 0x0cf7u16),
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#[cfg(target_arch = "x86_64")]
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&aml::AddressSpace::new_io(0x0d00u16, 0xffffu16),
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]),
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);
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let crs = if self.id == 0 {
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aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![
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&aml::AddressSpace::new_bus_number(0x0u16, 0x0u16),
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#[cfg(target_arch = "x86_64")]
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&aml::Io::new(0xcf8, 0xcf8, 1, 0x8),
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&aml::Memory32Fixed::new(
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true,
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self.mmio_config_address as u32,
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PCI_MMIO_CONFIG_SIZE as u32,
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),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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layout::MEM_32BIT_DEVICES_START.0 as u32,
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(layout::MEM_32BIT_DEVICES_START.0 + layout::MEM_32BIT_DEVICES_SIZE - 1)
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as u32,
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),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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self.start_of_device_area,
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self.end_of_device_area,
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),
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#[cfg(target_arch = "x86_64")]
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&aml::AddressSpace::new_io(0u16, 0x0cf7u16),
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#[cfg(target_arch = "x86_64")]
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&aml::AddressSpace::new_io(0x0d00u16, 0xffffu16),
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]),
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)
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} else {
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aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![
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&aml::AddressSpace::new_bus_number(0x0u16, 0x0u16),
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&aml::Memory32Fixed::new(
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true,
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self.mmio_config_address as u32,
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PCI_MMIO_CONFIG_SIZE as u32,
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),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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self.start_of_device_area,
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self.end_of_device_area,
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),
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]),
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)
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};
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pci_dsdt_inner_data.push(&crs);
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let mut pci_devices = Vec::new();
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