mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2024-10-02 11:35:46 +00:00
vmm: Only fill in PIO and 32-bit MMIO space on zero segment
Since each segment must have disjoint address spaces only advertise address space in the 32-bit range and the PIO address space on the default (zero) segment. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
parent
3059ba4305
commit
c118d7d7d3
@ -356,7 +356,8 @@ impl Aml for PciSegment {
|
|||||||
let pci_dsm = PciDsmMethod {};
|
let pci_dsm = PciDsmMethod {};
|
||||||
pci_dsdt_inner_data.push(&pci_dsm);
|
pci_dsdt_inner_data.push(&pci_dsm);
|
||||||
|
|
||||||
let crs = aml::Name::new(
|
let crs = if self.id == 0 {
|
||||||
|
aml::Name::new(
|
||||||
"_CRS".into(),
|
"_CRS".into(),
|
||||||
&aml::ResourceTemplate::new(vec![
|
&aml::ResourceTemplate::new(vec![
|
||||||
&aml::AddressSpace::new_bus_number(0x0u16, 0x0u16),
|
&aml::AddressSpace::new_bus_number(0x0u16, 0x0u16),
|
||||||
@ -371,7 +372,8 @@ impl Aml for PciSegment {
|
|||||||
aml::AddressSpaceCachable::NotCacheable,
|
aml::AddressSpaceCachable::NotCacheable,
|
||||||
true,
|
true,
|
||||||
layout::MEM_32BIT_DEVICES_START.0 as u32,
|
layout::MEM_32BIT_DEVICES_START.0 as u32,
|
||||||
(layout::MEM_32BIT_DEVICES_START.0 + layout::MEM_32BIT_DEVICES_SIZE - 1) as u32,
|
(layout::MEM_32BIT_DEVICES_START.0 + layout::MEM_32BIT_DEVICES_SIZE - 1)
|
||||||
|
as u32,
|
||||||
),
|
),
|
||||||
&aml::AddressSpace::new_memory(
|
&aml::AddressSpace::new_memory(
|
||||||
aml::AddressSpaceCachable::NotCacheable,
|
aml::AddressSpaceCachable::NotCacheable,
|
||||||
@ -384,7 +386,26 @@ impl Aml for PciSegment {
|
|||||||
#[cfg(target_arch = "x86_64")]
|
#[cfg(target_arch = "x86_64")]
|
||||||
&aml::AddressSpace::new_io(0x0d00u16, 0xffffu16),
|
&aml::AddressSpace::new_io(0x0d00u16, 0xffffu16),
|
||||||
]),
|
]),
|
||||||
);
|
)
|
||||||
|
} else {
|
||||||
|
aml::Name::new(
|
||||||
|
"_CRS".into(),
|
||||||
|
&aml::ResourceTemplate::new(vec![
|
||||||
|
&aml::AddressSpace::new_bus_number(0x0u16, 0x0u16),
|
||||||
|
&aml::Memory32Fixed::new(
|
||||||
|
true,
|
||||||
|
self.mmio_config_address as u32,
|
||||||
|
PCI_MMIO_CONFIG_SIZE as u32,
|
||||||
|
),
|
||||||
|
&aml::AddressSpace::new_memory(
|
||||||
|
aml::AddressSpaceCachable::NotCacheable,
|
||||||
|
true,
|
||||||
|
self.start_of_device_area,
|
||||||
|
self.end_of_device_area,
|
||||||
|
),
|
||||||
|
]),
|
||||||
|
)
|
||||||
|
};
|
||||||
pci_dsdt_inner_data.push(&crs);
|
pci_dsdt_inner_data.push(&crs);
|
||||||
|
|
||||||
let mut pci_devices = Vec::new();
|
let mut pci_devices = Vec::new();
|
||||||
|
Loading…
Reference in New Issue
Block a user