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pci: vfio: Split PCI capability parsing functions

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We need to split the parsing functions into one function dedicated to
the actual parsing and a second function for initializing the interrupt
type. This will be useful on the restore path as the parsing won't be
needed.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
This commit is contained in:
Sebastien Boeuf 2022-04-21 10:19:11 +02:00
parent f076819d81
commit f767e97fa5
1 changed files with 26 additions and 25 deletions
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51
pci/src/vfio.rs
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@ -581,25 +581,27 @@ impl VfioCommon {
Ok(()) Ok(())
} }
pub(crate) fn parse_msix_capabilities( pub(crate) fn parse_msix_capabilities(&mut self, cap: u8, vfio_wrapper: &dyn Vfio) -> MsixCap {
&mut self,
cap: u8,
interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
vfio_wrapper: &dyn Vfio,
bdf: PciBdf,
) {
let msg_ctl = vfio_wrapper.read_config_word((cap + 2).into()); let msg_ctl = vfio_wrapper.read_config_word((cap + 2).into());
let table = vfio_wrapper.read_config_dword((cap + 4).into()); let table = vfio_wrapper.read_config_dword((cap + 4).into());
let pba = vfio_wrapper.read_config_dword((cap + 8).into()); let pba = vfio_wrapper.read_config_dword((cap + 8).into());
let msix_cap = MsixCap { MsixCap {
msg_ctl, msg_ctl,
table, table,
pba, pba,
}; }
}
pub(crate) fn initialize_msix(
&mut self,
msix_cap: MsixCap,
cap_offset: u32,
interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
bdf: PciBdf,
) {
let interrupt_source_group = interrupt_manager let interrupt_source_group = interrupt_manager
.create_group(MsiIrqGroupConfig { .create_group(MsiIrqGroupConfig {
base: 0, base: 0,
@ -616,19 +618,21 @@ impl VfioCommon {
self.interrupt.msix = Some(VfioMsix { self.interrupt.msix = Some(VfioMsix {
bar: msix_config, bar: msix_config,
cap: msix_cap, cap: msix_cap,
cap_offset: cap.into(), cap_offset,
interrupt_source_group, interrupt_source_group,
}); });
} }
pub(crate) fn parse_msi_capabilities( pub(crate) fn parse_msi_capabilities(&mut self, cap: u8, vfio_wrapper: &dyn Vfio) -> u16 {
&mut self, vfio_wrapper.read_config_word((cap + 2).into())
cap: u8, }
interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
vfio_wrapper: &dyn Vfio,
) {
let msg_ctl = vfio_wrapper.read_config_word((cap + 2).into());
pub(crate) fn initialize_msi(
&mut self,
msg_ctl: u16,
cap_offset: u32,
interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
) {
let interrupt_source_group = interrupt_manager let interrupt_source_group = interrupt_manager
.create_group(MsiIrqGroupConfig { .create_group(MsiIrqGroupConfig {
base: 0, base: 0,
@ -640,7 +644,7 @@ impl VfioCommon {
self.interrupt.msi = Some(VfioMsi { self.interrupt.msi = Some(VfioMsi {
cfg: msi_config, cfg: msi_config,
cap_offset: cap.into(), cap_offset,
interrupt_source_group, interrupt_source_group,
}); });
} }
@ -662,7 +666,8 @@ impl VfioCommon {
if irq_info.count > 0 { if irq_info.count > 0 {
// Parse capability only if the VFIO device // Parse capability only if the VFIO device
// supports MSI. // supports MSI.
self.parse_msi_capabilities(cap_next, interrupt_manager, vfio_wrapper); let msg_ctl = self.parse_msi_capabilities(cap_next, vfio_wrapper);
self.initialize_msi(msg_ctl, cap_next as u32, interrupt_manager);
} }
} }
} }
@ -671,12 +676,8 @@ impl VfioCommon {
if irq_info.count > 0 { if irq_info.count > 0 {
// Parse capability only if the VFIO device // Parse capability only if the VFIO device
// supports MSI-X. // supports MSI-X.
self.parse_msix_capabilities( let msix_cap = self.parse_msix_capabilities(cap_next, vfio_wrapper);
cap_next, self.initialize_msix(msix_cap, cap_next as u32, interrupt_manager, bdf);
interrupt_manager,
vfio_wrapper,
bdf,
);
} }
} }
} }