Commit Graph

232 Commits

Author SHA1 Message Date
Michael Zhao
bf6920f774 aarch64: Optimize cpu-map creating code in FDT
The logic of determining VCPU index in creating `cpu-map` node of FDT
can be optimized.

The code is invoked when VCPU topology is specified.

Signed-off-by: Michael Zhao <michael.zhao@arm.com>
2022-02-22 09:21:00 +08:00
Michael Zhao
28d6bff340 aarch64: Simplify VCPU topology coding in FDT
In Flattened Device Tree (FDT) on AArch64, the VCPU topology is
represented by `cpu-map` node. The source code of creating the node
can be simplified.

Signed-off-by: Michael Zhao <michael.zhao@arm.com>
2022-02-22 09:21:00 +08:00
Sebastien Boeuf
2f0073544a arch: x86_64: tdx: Add a payload helper to TdHob
Adding a new method to the TdHob structure so that we can easily insert
a HOB_PAYLOAD_INFO_TABLE into the HOB.

Signed-off-by: Jiaqi Gao <jiaqi.gao@intel.com>
Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2022-02-04 13:57:56 +01:00
Sebastien Boeuf
2198baa547 arch: x86_64: tdx: Extend TDVF section types
Based on the recent updates of the TDVF specification introducing new
types of TDVF sections, let's extend the enum in our code.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2022-02-04 13:57:56 +01:00
Jianyong Wu
81c5855184 fdt: add PMU node to fdt
PMU node in fdt stores some important info like irq number.

Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
2022-01-21 17:59:36 +08:00
Jianyong Wu
53060874a7 vmm: Init PMU for vcpu when create vm
PMU is needed in guest for performance profiling, thus should be
enabled.

Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
2022-01-21 17:59:36 +08:00
Sebastien Boeuf
2acb50f752 arch: x86_64: tdx: Add ACPI table helper to TdHob
Adding a new method to the TdHob structure so that we can easily insert
a ACPI_TABLE_HOB into the HOB.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2022-01-20 16:50:55 +00:00
Sebastien Boeuf
4fda4ad6c9 arch, vmm: tdx: Remove TD_VMM_DATA mechanism
It's been decided the ACPI tables will be passed to the firmware in a
different way, rather than using TD_VMM_DATA. Since TD_VMM_DATA was
introduced for this purpose, there's no reason to keep it in our
codebase.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2022-01-20 16:50:55 +00:00
Wei Liu
c9983ff4ad arch: drop allow(clippy::transmute_ptr_to_ptr)
It is not needed.

Signed-off-by: Wei Liu <liuwe@microsoft.com>
2022-01-18 17:23:27 -08:00
Wei Liu
714b529bb2 arch: aarch64: drop unnecessary static lifetime
This also has the side effect for making access_redists_aux function
strictly more useful.

Signed-off-by: Wei Liu <liuwe@microsoft.com>
2022-01-18 17:23:27 -08:00
Wei Liu
99bcebad74 arch: aarch64: do not unnecessarily add mut keyword
Signed-off-by: Wei Liu <liuwe@microsoft.com>
2022-01-18 17:23:27 -08:00
Wei Liu
8155be2e6b arch: aarch64: vm_memory is not required when configuring vcpu
Drop the unused parameter throughout the code base.

Also take the chance to drop a needless clone.

No functional change intended.

Signed-off-by: Wei Liu <liuwe@microsoft.com>
2022-01-14 16:03:12 -08:00
Rob Bradford
ade8d71264 arch: aarch64: Fix beta clippy issue
error: unneeded late initalization
Error:    --> arch/src/aarch64/gic/gicv3_its.rs:127:9
    |
127 |         let attr: u64;
    |         ^^^^^^^^^^^^^^
    |
    = note: `-D clippy::needless-late-init` implied by `-D warnings`
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#needless_late_init
help: declare `attr` here
    |
128 |         let attr: u64 = if save {
    |         +++++++++++++++
help: remove the assignments from the branches
    |
129 ~             u64::from(kvm_bindings::KVM_DEV_ARM_ITS_SAVE_TABLES)
130 |         } else {
131 ~             u64::from(kvm_bindings::KVM_DEV_ARM_ITS_RESTORE_TABLES)
    |
help: add a semicolon after the `if` expression
    |
132 |         };
    |          +

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
2022-01-14 14:33:18 +00:00
Rob Bradford
3baebc1af0 arch: x86_64: Fix clippy (needless_late_init) issue
warning: unneeded late initalization
   --> arch/src/x86_64/mod.rs:318:17
    |
318 |                 let reg_val: u32;
    |                 ^^^^^^^^^^^^^^^^^
    |
    = note: `#[warn(clippy::needless_late_init)]` on by default
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#needless_late_init
help: declare `reg_val` here
    |
319 |                 let reg_val: u32 = match reg {
    |                 ++++++++++++++++++
help: remove the assignments from the `match` arms
    |
321 ~                         entry.eax
322 |                     }
323 |                     CpuidReg::EBX => {
324 ~                         entry.ebx
325 |                     }
326 |                     CpuidReg::ECX => {
  ...
help: add a semicolon after the `match` expression
    |
332 |                 };
    |                  +

warning: unneeded late initalization
   --> arch/src/x86_64/mod.rs:525:13
    |
525 |             let entry_compatible;
    |             ^^^^^^^^^^^^^^^^^^^^^
    |
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#needless_late_init
help: declare `entry_compatible` here
    |
526 |             let entry_compatible = match entry.compatible_check {
    |             ++++++++++++++++++++++
help: remove the assignments from the `match` arms
    |
530 ~                     src_vm_feature_bits_only == 0
531 |                 }
532 |                 CpuidCompatibleCheck::Equal => {
533 ~                     src_vm_feature == dest_vm_feature
534 |                 }
535 |                 CpuidCompatibleCheck::NumNotGreater => {

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
2022-01-07 08:16:26 -08:00
Henry Wang
90df54a245 aarch64: fdt: Create MSI mapping for PCI nodes
Each PCI device under a root complex is uniquely identified by its
Requester ID (AKA RID). A Requester ID is a triplet of a Bus number,
Device number, and Function number.

MSIs may be distinguished in part through the use of sideband data
accompanying writes. In the case of PCI devices, this sideband data
may be derived from the Requester ID. A mechanism is required to
associate a device with both the MSI controllers it can address,
and the sideband data that will be associated with its writes to
those controllers.

This commit adds the `msi-map` property for PCI nodes, therefore
creating MSI mapping for each PCI device.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-12-06 09:29:49 +00:00
Henry Wang
ca9a42ece8 aarch64: fdt: Create multiple PCI nodes based on PciSpaceInfo
This commit rewrites the `create_pci_node` in the FDT creator to
create multiple PCI nodes based on the vector of `PciSpaceInfo`,
and each PCI node in FDT reflects a PCI segment.

- The PCI MMIO config space, 32 bits PCI device space and 64 bits
PCI device space is re-calculated based on the `PciSpaceInfo` for
each PCI segment.
- A new FDT property `linux,pci-domain` is added.
- The virtio-iommu node is only created for the first PCI segment.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-12-06 09:29:49 +00:00
Henry Wang
2f8540da70 vmm: Rename PCI_MMIO_CONFIG_SIZE and move it to arch
The constant `PCI_MMIO_CONFIG_SIZE` defined in `vmm/pci_segment.rs`
describes the MMIO configuation size for each PCI segment. However,
this name conflicts with the `PCI_MMCONFIG_SIZE` defined in `layout.rs`
in the `arch` crate, which describes the memory size of the PCI MMIO
configuration region.

Therefore, this commit renames the `PCI_MMIO_CONFIG_SIZE` to
`PCI_MMIO_CONFIG_SIZE_PER_SEGMENT` and moves this constant from `vmm`
crate to `arch` crate.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-12-06 09:29:49 +00:00
Henry Wang
07bef815cc aarch64: Introduce struct PciSpaceInfo for FDT
Currently, a tuple containing PCI space start address and PCI space
size is used to pass the PCI space information to the FDT creator.
In order to support the multiple PCI segment for FDT, more information
such as the PCI segment ID should be passed to the FDT creator. If we
still use a tuple to store these information, the code flexibility and
readablity will be harmed.

To address this issue, this commit replaces the tuple containing the
PCI space information to a structure `PciSpaceInfo` and uses a vector
of `PciSpaceInfo` to store PCI space information for each segment, so
that multiple PCI segment information can be passed to the FDT together.

Note that the scope of this commit will only contain the refactor of
original code, the actual multiple PCI segments support will be in
following series, and for now `--platform num_pci_segments` should only
be 1.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-12-06 09:29:49 +00:00
Sebastien Boeuf
03a606c7ec arch, vmm: Place KVM identity map region after TSS region
In order to avoid the identity map region to conflict with a possible
firmware being placed in the last 4MiB of the 4GiB range, we must set
the address to a chosen location. And it makes the most sense to have
this region placed right after the TSS region.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2021-12-04 19:33:34 +00:00
Rob Bradford
348def9dfb arch, hypervisor, vmm: Explicitly place the TSS in the 32-bit space
Place the 3 page TSS at an explicit location in the 32-bit address space
to avoid conflicting with the loaded raw firmware.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
2021-12-03 16:53:56 +01:00
Rob Bradford
4f4eb3f6b8 arch: x86_64: Only reserve used 32-bit address space
Reduce the size of the reserved 32-bit address space to the range used
by both the PCI MMIO config data and the 32-bit PCI device space.

This avoids issues when using firmware that is loaded into the very top
of the 32-bit address space as the RAM conflicts with the reserved
memory.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
2021-12-02 16:42:01 +01:00
Rob Bradford
82d06c0efa vmm: Add support for booting raw binary (e.g. firmware) on x86-64
If the provided binary isn't an ELF binary assume that it is a firmware
to be loaded in directly. In this case we shouldn't program any of the
registers as KVM starts in that state.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
2021-11-30 13:39:36 +01:00
Wei Liu
03862314eb arch: x86_64: add safety comments for impl ByteValued
Group impl clauses together to avoid repetition.

Signed-off-by: Wei Liu <liuwe@microsoft.com>
2021-11-17 14:40:51 +00:00
Wei Liu
5813ce0307 arch: x86_64: drop test_apic_delivery_mode
This test generates an array of random numbers and then applies the same
trivial algorithm twice -- once in set_apic_delivery_mode and another
time in an anonymous function.

Its usefulness is limited. Drop it to remove one unsafe in code.

Signed-off-by: Wei Liu <liuwe@microsoft.com>
2021-11-16 13:49:36 +00:00
Wei Liu
a4d8616676 arch: x86_64: tdx: drop one unsafe call in code
Implement Default trait for TdvfDescriptor and drop one unsafe in code.

No functional change.

Signed-off-by: Wei Liu <liuwe@microsoft.com>
2021-11-10 17:46:21 +01:00
Sebastien Boeuf
58d8206e2b migration: Use MemoryManager restore code path
Instead of creating a MemoryManager from scratch, let's reuse the same
code path used by snapshot/restore, so that memory regions are created
identically to what they were on the source VM.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2021-10-06 18:35:49 -07:00
Sebastien Boeuf
5b177b205b arch, vmm: Extend the data being snapshot
Storing multiple data coming from the MemoryManager in order to be able
to restore without creating everything from scratch.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2021-10-06 18:35:49 -07:00
Sebastien Boeuf
84a741a3fa arch: x86_64: tdx: Add TD_VMM_DATA support
Adding the definitions and helpers to build TD_VMM_DATA regions as part
of the TD_HOB.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2021-09-30 06:35:55 -07:00
Rob Bradford
1a2d0e6dd8 build: bump linux-loader from 0.3.0 to 0.4.0
Requires manual change to command line loading.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
2021-09-24 09:11:57 +00:00
Michael Zhao
b30ddc0837 aarch64: Refactor AArch64 GIC space definitions
Move the definition of MSI space to layout.rs, so other crates can
reference it. Now it is needed by virtio-iommu.

Signed-off-by: Michael Zhao <michael.zhao@arm.com>
2021-09-17 12:19:46 +02:00
Michael Zhao
253c06d3ba arch/aarch64: Add virtio-iommu device in FDT
Add a virtio-iommu node into FDT if iommu option is turned on. Now we
support only one virtio-iommu device.

Signed-off-by: Michael Zhao <michael.zhao@arm.com>
2021-09-17 12:19:46 +02:00
Henry Wang
46c60183cd arch, vmm: Implement GIC Pausable trait
This commit implements the GIC (including both GICv3 and GICv3ITS)
Pausable trait. The pause of device manager will trigger a "pause"
of GIC, where we flush GIC pending tables and ITS tables to the
guest RAM.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-09-02 15:18:41 +01:00
Henry Wang
c9cc97e9a0 arch: Add NUMA configuration to FDT memory node
Based on `--memory-zone` and `--numa` param in the Cloud Hypervisor
cmdline, the NUMA memory configuration is described. This commit
adds such NUMA memory configuration to the FDT memory node.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-08-12 10:49:02 +02:00
Henry Wang
f3197c3833 arch: Add numa-node-id property to CPU node
For the purpose of identification, each NUMA node is associated
with a unique token known as a `numa-node-id`. For the purpose of
device tree binding, a `numa-node-id` is a 32-bit integer.

The CPU node is associated with a NUMA node by the presence of a
`numa-node-id` property which contains the node id of the device.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-08-12 10:49:02 +02:00
Henry Wang
5a0a4bc505 arch: Add optional distance-map node to FDT
The optional device tree node distance-map describes the relative
distance (memory latency) between all NUMA nodes.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-08-12 10:49:02 +02:00
Henry Wang
165364e08b vmm: Move NUMA node data structures to arch
This is to make sure the NUMA node data structures can be accessed
both from the `vmm` crate and `arch` crate.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-08-12 10:49:02 +02:00
Henry Wang
447c986916 aarch64: Add optional cpu-map node in device tree
The Arm CPU topology is defined within the `cpu-map` node, which is
a direct child of the cpus node and provides a container where the
actual topology nodes are listed.

This commit adds an optional cpu-map node in device tree, based on
the Cloud Hypervisor command line vCPU topology information.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-08-05 21:19:16 +08:00
Henry Wang
7fb980f17b arch, vmm: Pass cpu topology configuation to FDT
In an Arm system, the hierarchy of CPUs is defined through three
entities that are used to describe the layout of physical CPUs in
the system:

- cluster
- core
- thread

All these three entities have their own FDT node field. Therefore,
This commit adds an AArch64-specific helper to pass the config from
the Cloud Hypervisor command line to the `configure_system`, where
eventually the `create_fdt` is called.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-08-05 21:19:16 +08:00
Bo Chen
2723995cfa arch: Support fine-grained CPUID compatibility check
To support different CPUID entry semantics, we now allow to
specify the compatible condition for each feature entry. Most entries
are considered compatible when they are "bitwise subset", with few
exceptions: 1. "equal", e.g. EBX/ECX/EDX of leaf `0x4000_0000` (KVM
CPUID SIGNATURE); 2. "smaller or equal as a number", e.g. EAX of leaf
`0x7` and leaf `0x4000_0000`;

Signed-off-by: Bo Chen <chen.bo@intel.com>
2021-07-28 09:26:02 +02:00
Bo Chen
6d9c1eb638 arch, vmm: Add CPUID check to the 'Config' step of live migration
We now send not only the 'VmConfig' at the 'Command::Config' step of
live migration, but also send the 'common CPUID'. In this way, we can
check the compatibility of CPUID features between the source and
destination VMs, and abort live migration early if needed.

Signed-off-by: Bo Chen <chen.bo@intel.com>
2021-07-28 09:26:02 +02:00
Bo Chen
569be6e706 arch, vmm: Move "generate_common_cpuid" from "CpuManager" to "arch"
This refactoring ensures all CPUID related operations are centralized in
`arch::x86_64` module, and exposes only two related public functions to
the vmm crate, e.g. `generate_common_cpuid` and `configure_vcpu`.

Signed-off-by: Bo Chen <chen.bo@intel.com>
2021-07-19 09:59:34 -07:00
Sebastien Boeuf
7f507dd77d arch: x86_64: tdx: Fix HobHandoffInfoTable
The handoff table was missing the boot_mode field.

Suggested-by: Jiaqi Gao <jiaqi.gao@intel.com>
Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2021-07-09 14:56:28 -07:00
Sebastien Boeuf
9aedabe11e sgx: Add mandatory id field to SgxEpcConfig
In order to uniquely identify each SGX EPC section, we introduce a
mandatory option `id` to the `--sgx-epc` parameter.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2021-07-09 14:45:30 +02:00
Henry Wang
c46441c937 build: bump vm-fdt from bbfd1e7 to 02d1b8f
Bumps [vm-fdt](https://github.com/rust-vmm/vm-fdt) from `bbfd1e7` to `02d1b8f`.
- [Release notes](https://github.com/rust-vmm/vm-fdt/releases)
- [Commits](bbfd1e7719...02d1b8fde2)

---
updated-dependencies:
- dependency-name: vm-fdt
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-07-07 09:55:18 +02:00
Sebastien Boeuf
5b6d424a77 arch, vmm: Fix TDVF section handling
This patch fixes a few things to support TDVF correctly.

The HOB memory resources must contain EFI_RESOURCE_ATTRIBUTE_ENCRYPTED
attribute.

Any section with a base address within the already allocated guest RAM
must not be allocated.

The list of TD_HOB memory resources should contain both TempMem and
TdHob sections as well.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2021-07-06 11:47:43 +02:00
Jianyong Wu
8744162a0e arch: gic: Change restoring order of GICR register
If GICR_CTLR is restored before GICR_PROPBASER and GICR_PENDBASER,
the restoring of the latter registers will fail, as the LPI enable
bit is already set in GICR_CTLR. Therefore, in this commit, the
order of restoring GICR registers is changed.

Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
2021-07-05 22:51:56 +02:00
Henry Wang
6dcf9f6588 arch: aarch64: Implement ITS Snapshottable trait
This commit implements the GicV3Its Snapshottable trait, including:

- GicV3Its state: GIC registers and ITS registers
- Save/restore logic of GicV3Its state

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-07-05 22:51:56 +02:00
Henry Wang
4440671739 arch: gic: Prepare helper functions to access ITS
This commit implements two helper functions `gicv3_its_attr_access`
and `gicv3_its_tables_access` to access ITS device attributes and
ITS tables.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-07-05 22:51:56 +02:00
Henry Wang
957d3deeea arch: gic: Extend GicV3Its with its_device field
In current code, the ITS device fd of GICv3 will be lost after the
creation of GIC. This commit adds a new `its_device` field for the
`GicV3Its` struct, which will be useful to save the ITS device fd.
This fd will be used in restoring the ITS device.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
2021-07-05 22:51:56 +02:00
Michael Zhao
45c4d1a06e aarch64: Reduce UEFI space size to 4 MiB
UEFI need to be loaded to a flash area at the beginning of guest memory
address space. To simulate the flash, we take a piece of RAM and hide
it to the guest. As this is a temporary solution, the hiden RAM for UEFI
should be as little as possible. The size was 64 MiB, that's too much,
4 MiB is enough.

The down side of such simulation is that there is a gap (4 MiB) between
the memory size in VMM's view and that in guest's view. This is to be
fixed by implementing a flash device in future.

Signed-off-by: Michael Zhao <michael.zhao@arm.com>
2021-06-24 13:13:27 +01:00