Sebastien Boeuf c2ae380503 pci: Refine detection of BAR reprogramming ... The current code was always considering 0xffffffff being written to the register as a sign it was expecting to get the size, hence the BAR reprogramming detection was stating this case was not a reprogramming case. Problem is, if the value 0xffffffff is directed at a 64bits BAR, this might be the high or low part of a 64bits address which is meant to be the new address of the BAR, which means we would miss the detection of the BAR being reprogrammed here. This commit improves the code using finer granularity checks in order to detect this corner case correctly. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>		2020-01-09 08:05:35 +01:00
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bus.rs	vmm: Conditionally update ioeventfds for virtio PCI device	2019-10-31 09:30:59 +01:00
configuration.rs	pci: Refine detection of BAR reprogramming	2020-01-09 08:05:35 +01:00
device.rs	pci: Remove ioeventfds() from PciDevice trait	2019-10-31 09:30:59 +01:00
lib.rs	pci: Remove KVM dependency	2019-10-29 20:09:04 -07:00
msi.rs	pci: msi: Fix MSG_CTL update through 32 bits write	2019-12-04 08:48:17 +01:00
msix.rs	pci: Add MSI-X helper to check if interrupts are enabled	2019-08-08 17:38:47 +01:00