5 Commits

Author	SHA1	Message	Date
Tim Wiederhake	986be35f2e	cpu_map: Sort cpu features ... Some feature words were not sorted correctly. Signed-off-by: Tim Wiederhake <twiederh@redhat.com> Reviewed-by: Jiri Denemark <jdenemar@redhat.com>	2024-02-20 17:29:27 +01:00
Jiri Denemark	eb1b551d21	cpu: Add support for "stibp" x86_64 feature ... QEMU commit v3.1.0-4-g0e89165829 KVM patch: https://lore.kernel.org/lkml/20181205191956.31480-1-ehabkost@redhat.com/ Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Ján Tomko <jtomko@redhat.com>	2018-12-17 17:27:32 +01:00
Jiri Denemark	9813081119	cpu_map: Add features for Icelake CPUs ... QEMU commits: e37a5c7fa4 (v2.12.0) i386: Add Intel Processor Trace feature support c2f193b538 (v2.7.0) target-i386: Add support for UMIP and RDPID CPUID bits aff9e6e46a (v2.12.0) x86/cpu: Enable new SSE/AVX/AVX512 cpu features f77543772d (v2.9.0) x86: add AVX512_VPOPCNTDQ features 5131dc433d (v3.1.0) i386: Add CPUID bit for PCONFIG 59a80a19ca (v3.1.0) i386: Add CPUID bit for WBNOINVD Signed-off-by: Jiri Denemark <jdenemar@redhat.com>	2018-09-19 14:05:59 +02:00
Jiri Denemark	7bb4ce9761	cpu: Add Broadwell-IBRS CPU model ... This is a variant of Broadwell with indirect branch prediction protection. The only difference between Broadwell and Broadwell-IBRS is the added "spec-ctrl" feature. The Broadwell-IBRS model in QEMU is a bit different since Broadwell got several additional features since we added it in cpu_map.xml: abm, arat, f16c, rdrand, vme, xsaveopt Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Pavel Hrdina <phrdina@redhat.com>	2018-01-17 17:07:04 +01:00
Jiri Denemark	edcab4d0a4	cputest: Add data for updated Intel(R) Core(TM) i7-5600U CPU ... The CPU contains the updated microcode for CVE-2017-5715. Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Pavel Hrdina <phrdina@redhat.com>	2018-01-17 17:07:02 +01:00