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ae16c95f1b
This patch adds support and documentation for a generalized hardware cache event called cache_l1d perf event. Signed-off-by: Nitesh Konkar <nitkon12@linux.vnet.ibm.com>
34 lines
1.1 KiB
XML
34 lines
1.1 KiB
XML
<domain type='qemu'>
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<name>foo</name>
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<uuid>c7a5fdbd-edaf-9455-926a-d65c16db1809</uuid>
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<memory unit='KiB'>219136</memory>
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<currentMemory unit='KiB'>219136</currentMemory>
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<vcpu placement='static'>1</vcpu>
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<os>
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<type arch='i686' machine='pc'>hvm</type>
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<boot dev='hd'/>
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</os>
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<clock offset='utc'/>
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<on_poweroff>destroy</on_poweroff>
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<on_reboot>restart</on_reboot>
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<on_crash>destroy</on_crash>
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<perf>
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<event name='cmt' enabled='yes'/>
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<event name='mbmt' enabled='no'/>
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<event name='mbml' enabled='yes'/>
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<event name='cpu_cycles' enabled='no'/>
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<event name='instructions' enabled='yes'/>
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<event name='cache_references' enabled='no'/>
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<event name='cache_misses' enabled='no'/>
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<event name='branch_instructions' enabled='yes'/>
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<event name='branch_misses' enabled='yes'/>
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<event name='bus_cycles' enabled='yes'/>
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<event name='stalled_cycles_frontend' enabled='yes'/>
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<event name='stalled_cycles_backend' enabled='yes'/>
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<event name='ref_cpu_cycles' enabled='yes'/>
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<event name='cache_l1d' enabled='yes'/>
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</perf>
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<devices>
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</devices>
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</domain>
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