2020-06-03 19:23:56 +00:00
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// Copyright © 2019 Intel Corporation
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//
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2020-06-26 00:06:14 +00:00
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// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
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2020-06-03 19:23:56 +00:00
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//
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2020-06-28 16:32:56 +00:00
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// Copyright © 2020, Microsoft Corporation
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2020-06-03 19:23:56 +00:00
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//
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// Copyright 2018-2019 CrowdStrike, Inc.
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//
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2020-06-26 00:06:14 +00:00
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//
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2020-06-03 19:23:56 +00:00
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#[cfg(target_arch = "aarch64")]
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2022-07-28 03:35:21 +00:00
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use crate::aarch64::{RegList, StandardRegisters, VcpuInit};
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2022-07-14 20:59:27 +00:00
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#[cfg(target_arch = "x86_64")]
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2022-07-19 21:41:00 +00:00
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use crate::arch::x86::{
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CpuIdEntry, FpuState, LapicState, MsrEntry, SpecialRegisters, StandardRegisters,
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};
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2022-05-11 16:21:25 +00:00
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#[cfg(feature = "tdx")]
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use crate::kvm::{TdxExitDetails, TdxExitStatus};
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2020-12-03 23:24:57 +00:00
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use crate::CpuState;
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use crate::MpState;
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2020-06-03 19:23:56 +00:00
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use thiserror::Error;
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2022-07-20 22:02:43 +00:00
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#[cfg(target_arch = "x86_64")]
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2022-02-20 02:49:25 +00:00
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use vm_memory::GuestAddress;
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2020-06-03 19:23:56 +00:00
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#[derive(Error, Debug)]
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///
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/// Enum for CPU error
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pub enum HypervisorCpuError {
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///
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/// Setting standard registers error
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///
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#[error("Failed to set standard register: {0}")]
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SetStandardRegs(#[source] anyhow::Error),
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///
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/// Setting standard registers error
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///
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#[error("Failed to get standard registers: {0}")]
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GetStandardRegs(#[source] anyhow::Error),
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///
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/// Setting special register error
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///
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#[error("Failed to set special registers: {0}")]
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SetSpecialRegs(#[source] anyhow::Error),
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///
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/// Getting standard register error
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///
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#[error("Failed to get special registers: {0}")]
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GetSpecialRegs(#[source] anyhow::Error),
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///
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/// Setting floating point registers error
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///
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#[error("Failed to set special register: {0}")]
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SetFloatingPointRegs(#[source] anyhow::Error),
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///
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/// Getting floating point register error
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///
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#[error("Failed to get special register: {0}")]
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GetFloatingPointRegs(#[source] anyhow::Error),
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///
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/// Setting Cpuid error
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///
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#[error("Failed to set Cpuid: {0}")]
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SetCpuid(#[source] anyhow::Error),
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///
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/// Getting Cpuid error
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///
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#[error("Failed to get Cpuid: {0}")]
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GetCpuid(#[source] anyhow::Error),
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///
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/// Setting lapic state error
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///
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#[error("Failed to set Lapic state: {0}")]
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SetLapicState(#[source] anyhow::Error),
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///
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/// Getting Lapic state error
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///
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#[error("Failed to get Lapic state: {0}")]
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GetlapicState(#[source] anyhow::Error),
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///
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/// Setting MSR entries error
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///
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#[error("Failed to set Msr entries: {0}")]
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SetMsrEntries(#[source] anyhow::Error),
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///
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/// Getting Msr entries error
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///
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#[error("Failed to get Msr entries: {0}")]
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GetMsrEntries(#[source] anyhow::Error),
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///
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/// Setting MSR entries error
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///
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#[error("Failed to set MP state: {0}")]
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SetMpState(#[source] anyhow::Error),
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///
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/// Getting Msr entries error
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///
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#[error("Failed to get MP state: {0}")]
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GetMpState(#[source] anyhow::Error),
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///
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/// Setting Saved Processor Extended States error
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///
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#[error("Failed to set Saved Processor Extended States: {0}")]
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SetXsaveState(#[source] anyhow::Error),
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///
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/// Getting Saved Processor Extended States error
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///
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#[error("Failed to get Saved Processor Extended States: {0}")]
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GetXsaveState(#[source] anyhow::Error),
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///
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/// Setting Extended Control Registers error
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///
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#[error("Failed to set Extended Control Registers: {0}")]
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SetXcsr(#[source] anyhow::Error),
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///
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/// Getting Extended Control Registers error
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///
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#[error("Failed to get Extended Control Registers: {0}")]
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GetXcsr(#[source] anyhow::Error),
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///
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/// Running Vcpu error
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///
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#[error("Failed to run vcpu: {0}")]
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RunVcpu(#[source] anyhow::Error),
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///
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/// Getting Vcpu events error
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///
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#[error("Failed to get Vcpu events: {0}")]
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GetVcpuEvents(#[source] anyhow::Error),
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///
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2020-06-24 14:52:41 +00:00
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/// Setting Vcpu events error
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///
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#[error("Failed to set Vcpu events: {0}")]
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SetVcpuEvents(#[source] anyhow::Error),
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///
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2020-06-03 19:23:56 +00:00
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/// Vcpu Init error
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///
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#[error("Failed to init vcpu: {0}")]
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VcpuInit(#[source] anyhow::Error),
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///
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/// Setting one reg error
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///
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#[error("Failed to init vcpu: {0}")]
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2020-10-07 14:45:25 +00:00
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SetRegister(#[source] anyhow::Error),
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2020-06-03 19:23:56 +00:00
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///
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/// Getting one reg error
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///
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#[error("Failed to init vcpu: {0}")]
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2020-10-07 14:45:25 +00:00
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GetRegister(#[source] anyhow::Error),
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2020-06-23 14:42:00 +00:00
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///
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/// Getting guest clock paused error
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///
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#[error("Failed to notify guest its clock was paused: {0}")]
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NotifyGuestClockPaused(#[source] anyhow::Error),
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2020-09-15 15:15:50 +00:00
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///
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2020-12-03 23:24:57 +00:00
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/// Setting debug register error
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///
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#[error("Failed to set debug registers: {0}")]
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SetDebugRegs(#[source] anyhow::Error),
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///
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/// Getting debug register error
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///
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#[error("Failed to get debug registers: {0}")]
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GetDebugRegs(#[source] anyhow::Error),
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///
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2021-09-30 19:41:32 +00:00
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/// Setting misc register error
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///
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#[error("Failed to set misc registers: {0}")]
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SetMiscRegs(#[source] anyhow::Error),
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///
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/// Getting misc register error
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///
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#[error("Failed to get misc registers: {0}")]
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GetMiscRegs(#[source] anyhow::Error),
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///
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2020-12-03 23:24:57 +00:00
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/// Write to Guest Mem
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///
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#[error("Failed to write to Guest Mem at: {0}")]
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GuestMemWrite(#[source] anyhow::Error),
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2020-09-15 15:15:50 +00:00
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/// Enabling HyperV SynIC error
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///
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#[error("Failed to enable HyperV SynIC")]
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2021-03-25 17:01:21 +00:00
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EnableHyperVSyncIc(#[source] anyhow::Error),
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2020-08-28 09:06:54 +00:00
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///
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2020-08-30 08:44:39 +00:00
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/// Getting AArch64 core register error
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///
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#[error("Failed to get core register: {0}")]
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GetCoreRegister(#[source] anyhow::Error),
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///
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/// Setting AArch64 core register error
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///
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#[error("Failed to set core register: {0}")]
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SetCoreRegister(#[source] anyhow::Error),
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///
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/// Getting AArch64 registers list error
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///
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#[error("Failed to retrieve list of registers: {0}")]
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GetRegList(#[source] anyhow::Error),
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///
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2020-08-28 09:06:54 +00:00
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/// Getting AArch64 system register error
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///
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#[error("Failed to get system register: {0}")]
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GetSysRegister(#[source] anyhow::Error),
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2020-08-30 08:44:39 +00:00
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///
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/// Setting AArch64 system register error
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///
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#[error("Failed to set system register: {0}")]
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SetSysRegister(#[source] anyhow::Error),
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2021-03-01 18:07:02 +00:00
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///
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/// GVA translation error
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///
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#[error("Failed to translate GVA: {0}")]
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2021-03-25 17:01:21 +00:00
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TranslateVirtualAddress(#[source] anyhow::Error),
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2021-02-12 15:17:18 +00:00
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///
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2022-01-11 06:39:42 +00:00
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/// Set cpu attribute error
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///
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#[error("Failed to set vcpu attribute: {0}")]
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SetVcpuAttribute(#[source] anyhow::Error),
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///
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/// Check if cpu has a certain attribute error
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///
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#[error("Failed to check if vcpu has attribute: {0}")]
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HasVcpuAttribute(#[source] anyhow::Error),
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///
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2021-02-12 15:17:18 +00:00
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/// Failed to initialize TDX on CPU
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///
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#[cfg(feature = "tdx")]
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#[error("Failed to initialize TDX: {0}")]
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InitializeTdx(#[source] std::io::Error),
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2022-02-16 14:39:54 +00:00
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///
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/// Unknown TDX VM call
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///
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#[cfg(feature = "tdx")]
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#[error("Unknown TDX VM call")]
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UnknownTdxVmCall,
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2022-07-20 11:42:24 +00:00
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#[cfg(target_arch = "aarch64")]
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///
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/// Failed to intialize PMU
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///
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#[error("Failed to initialize PMU")]
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InitializePmu,
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2020-06-03 19:23:56 +00:00
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}
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2020-07-03 14:27:53 +00:00
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#[derive(Debug)]
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pub enum VmExit<'a> {
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#[cfg(target_arch = "x86_64")]
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IoOut(u16 /* port */, &'a [u8] /* data */),
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#[cfg(target_arch = "x86_64")]
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IoIn(u16 /* port */, &'a mut [u8] /* data */),
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#[cfg(target_arch = "x86_64")]
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IoapicEoi(u8 /* vector */),
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MmioRead(u64 /* address */, &'a mut [u8]),
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MmioWrite(u64 /* address */, &'a [u8]),
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Ignore,
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Reset,
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2020-10-30 13:34:16 +00:00
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Shutdown,
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2020-09-15 15:17:23 +00:00
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Hyperv,
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2022-02-16 14:39:54 +00:00
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#[cfg(feature = "tdx")]
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Tdx,
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2022-01-30 10:26:32 +00:00
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#[cfg(feature = "kvm")]
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Debug,
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2020-07-03 14:27:53 +00:00
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}
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2020-06-03 19:23:56 +00:00
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///
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/// Result type for returning from a function
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///
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pub type Result<T> = anyhow::Result<T, HypervisorCpuError>;
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///
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/// Trait to represent a generic Vcpu
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///
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pub trait Vcpu: Send + Sync {
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///
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/// Returns the vCPU general purpose registers.
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///
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fn get_regs(&self) -> Result<StandardRegisters>;
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///
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/// Sets the vCPU general purpose registers.
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///
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fn set_regs(&self, regs: &StandardRegisters) -> Result<()>;
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#[cfg(target_arch = "x86_64")]
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///
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/// Returns the vCPU special registers.
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///
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fn get_sregs(&self) -> Result<SpecialRegisters>;
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#[cfg(target_arch = "x86_64")]
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///
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/// Sets the vCPU special registers
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///
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fn set_sregs(&self, sregs: &SpecialRegisters) -> Result<()>;
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#[cfg(target_arch = "x86_64")]
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///
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/// Returns the floating point state (FPU) from the vCPU.
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///
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fn get_fpu(&self) -> Result<FpuState>;
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#[cfg(target_arch = "x86_64")]
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///
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/// Set the floating point state (FPU) of a vCPU
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///
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fn set_fpu(&self, fpu: &FpuState) -> Result<()>;
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#[cfg(target_arch = "x86_64")]
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///
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/// X86 specific call to setup the CPUID registers.
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///
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2022-07-15 10:20:07 +00:00
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fn set_cpuid2(&self, cpuid: &[CpuIdEntry]) -> Result<()>;
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2020-06-03 19:23:56 +00:00
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#[cfg(target_arch = "x86_64")]
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///
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2020-09-15 15:15:50 +00:00
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/// X86 specific call to enable HyperV SynIC
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///
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fn enable_hyperv_synic(&self) -> Result<()>;
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#[cfg(target_arch = "x86_64")]
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///
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2020-06-03 19:23:56 +00:00
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/// X86 specific call to retrieve the CPUID registers.
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///
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2022-07-15 10:20:07 +00:00
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fn get_cpuid2(&self, num_entries: usize) -> Result<Vec<CpuIdEntry>>;
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2020-06-03 19:23:56 +00:00
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#[cfg(target_arch = "x86_64")]
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///
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/// Returns the state of the LAPIC (Local Advanced Programmable Interrupt Controller).
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///
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fn get_lapic(&self) -> Result<LapicState>;
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#[cfg(target_arch = "x86_64")]
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///
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/// Sets the state of the LAPIC (Local Advanced Programmable Interrupt Controller).
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///
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fn set_lapic(&self, lapic: &LapicState) -> Result<()>;
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#[cfg(target_arch = "x86_64")]
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///
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/// Returns the model-specific registers (MSR) for this vCPU.
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///
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2022-07-19 09:51:18 +00:00
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fn get_msrs(&self, msrs: &mut Vec<MsrEntry>) -> Result<usize>;
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2020-06-03 19:23:56 +00:00
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#[cfg(target_arch = "x86_64")]
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///
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/// Setup the model-specific registers (MSR) for this vCPU.
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///
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2022-07-19 09:51:18 +00:00
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fn set_msrs(&self, msrs: &[MsrEntry]) -> Result<usize>;
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2020-06-03 19:23:56 +00:00
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///
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/// Returns the vcpu's current "multiprocessing state".
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///
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fn get_mp_state(&self) -> Result<MpState>;
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///
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/// Sets the vcpu's current "multiprocessing state".
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///
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fn set_mp_state(&self, mp_state: MpState) -> Result<()>;
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2022-07-20 22:02:43 +00:00
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|
#[cfg(target_arch = "x86_64")]
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2020-06-24 14:52:41 +00:00
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///
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2020-06-23 14:42:00 +00:00
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/// Let the guest know that it has been paused, which prevents from
|
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/// potential soft lockups when being resumed.
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///
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2022-07-20 22:02:43 +00:00
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fn notify_guest_clock_paused(&self) -> Result<()> {
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|
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Ok(())
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}
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#[cfg(target_arch = "x86_64")]
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2022-02-20 02:49:25 +00:00
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///
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/// Sets debug registers to set hardware breakpoints and/or enable single step.
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///
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2022-07-20 22:02:43 +00:00
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|
|
fn set_guest_debug(&self, _addrs: &[GuestAddress], _singlestep: bool) -> Result<()> {
|
|
|
|
Err(HypervisorCpuError::SetDebugRegs(anyhow!("unimplemented")))
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|
|
|
}
|
2020-06-03 19:23:56 +00:00
|
|
|
///
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|
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|
/// Sets the type of CPU to be exposed to the guest and optional features.
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///
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2022-06-21 03:39:54 +00:00
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|
#[cfg(target_arch = "aarch64")]
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2020-06-03 19:23:56 +00:00
|
|
|
fn vcpu_init(&self, kvi: &VcpuInit) -> Result<()>;
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|
|
///
|
2020-08-30 08:44:39 +00:00
|
|
|
/// Gets a list of the guest registers that are supported for the
|
|
|
|
/// KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.
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|
|
///
|
2022-06-21 03:39:54 +00:00
|
|
|
#[cfg(target_arch = "aarch64")]
|
2020-08-30 08:44:39 +00:00
|
|
|
fn get_reg_list(&self, reg_list: &mut RegList) -> Result<()>;
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|
|
|
///
|
2022-07-28 06:52:34 +00:00
|
|
|
/// Gets the value of a system register
|
|
|
|
///
|
|
|
|
#[cfg(target_arch = "aarch64")]
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|
|
|
fn get_sys_reg(&self, sys_reg: u32) -> Result<u64>;
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|
|
///
|
2022-06-06 07:17:59 +00:00
|
|
|
/// Configure core registers for a given CPU.
|
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|
|
///
|
2022-06-21 03:39:54 +00:00
|
|
|
#[cfg(target_arch = "aarch64")]
|
2022-06-06 07:17:59 +00:00
|
|
|
fn setup_regs(&self, cpu_id: u8, boot_ip: u64, fdt_start: u64) -> Result<()>;
|
|
|
|
///
|
2022-07-20 11:42:24 +00:00
|
|
|
/// Check if the CPU supports PMU
|
|
|
|
///
|
|
|
|
#[cfg(target_arch = "aarch64")]
|
|
|
|
fn has_pmu_support(&self) -> bool;
|
|
|
|
///
|
|
|
|
/// Initialize PMU
|
|
|
|
///
|
|
|
|
#[cfg(target_arch = "aarch64")]
|
|
|
|
fn init_pmu(&self, irq: u32) -> Result<()>;
|
|
|
|
///
|
2020-07-03 08:54:36 +00:00
|
|
|
/// Retrieve the vCPU state.
|
|
|
|
/// This function is necessary to snapshot the VM
|
2020-06-03 19:23:56 +00:00
|
|
|
///
|
2020-07-03 08:54:36 +00:00
|
|
|
fn state(&self) -> Result<CpuState>;
|
2020-06-03 19:23:56 +00:00
|
|
|
///
|
2020-07-03 08:54:36 +00:00
|
|
|
/// Set the vCPU state.
|
2020-06-03 19:23:56 +00:00
|
|
|
/// This function is required when restoring the VM
|
|
|
|
///
|
2020-07-03 08:54:36 +00:00
|
|
|
fn set_state(&self, state: &CpuState) -> Result<()>;
|
2020-07-03 14:27:53 +00:00
|
|
|
///
|
|
|
|
/// Triggers the running of the current virtual CPU returning an exit reason.
|
|
|
|
///
|
|
|
|
fn run(&self) -> std::result::Result<VmExit, HypervisorCpuError>;
|
2022-02-20 02:44:25 +00:00
|
|
|
#[cfg(target_arch = "x86_64")]
|
2021-03-01 18:07:02 +00:00
|
|
|
///
|
|
|
|
/// Translate guest virtual address to guest physical address
|
|
|
|
///
|
2022-02-19 05:52:48 +00:00
|
|
|
fn translate_gva(&self, gva: u64, flags: u64) -> Result<(u64, u32)>;
|
2021-02-12 15:17:18 +00:00
|
|
|
///
|
|
|
|
/// Initialize TDX support on the vCPU
|
|
|
|
///
|
|
|
|
#[cfg(feature = "tdx")]
|
|
|
|
fn tdx_init(&self, hob_address: u64) -> Result<()>;
|
2022-02-07 14:36:39 +00:00
|
|
|
///
|
|
|
|
/// Set the "immediate_exit" state
|
|
|
|
///
|
2022-07-20 22:02:43 +00:00
|
|
|
fn set_immediate_exit(&self, _exit: bool) {}
|
2022-02-16 14:39:54 +00:00
|
|
|
#[cfg(feature = "tdx")]
|
|
|
|
///
|
|
|
|
/// Returns the details about TDX exit reason
|
|
|
|
///
|
|
|
|
fn get_tdx_exit_details(&mut self) -> Result<TdxExitDetails>;
|
|
|
|
#[cfg(feature = "tdx")]
|
|
|
|
///
|
|
|
|
/// Set the status code for TDX exit
|
|
|
|
///
|
|
|
|
fn set_tdx_status(&mut self, status: TdxExitStatus);
|
2022-07-08 14:08:10 +00:00
|
|
|
#[cfg(target_arch = "x86_64")]
|
|
|
|
///
|
|
|
|
/// Return the list of initial MSR entries for a VCPU
|
|
|
|
///
|
2022-07-19 09:51:18 +00:00
|
|
|
fn boot_msr_entries(&self) -> Vec<MsrEntry>;
|
2020-06-03 19:23:56 +00:00
|
|
|
}
|