Commit Graph

376 Commits

Author SHA1 Message Date
Rob Bradford
2bf6f9300a hypervisor: Remove derivations conditional on non-existant feature
The "with-serde" feature does not exist so these [#derive(..)]
statements are never compiled in.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
2024-05-08 08:10:28 +00:00
Muminul Islam
4847f5c4f6 hypervisor: implement clock data for MSHV
This PR implement time reference for Microsoft
Hypervisor based partition/VM.

Signed-off-by: Muminul Islam <muislam@microsoft.com>
2024-04-29 16:46:26 +00:00
Rob Bradford
b89657ea22 hypervisor, vmm: Don't re-export the contents of mshv_bindings::*
The contents of this crate may change and cause conflicts - re-exporting
the contents is unnecessary.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
2024-04-25 20:53:53 +00:00
Rob Bradford
7be69edf51 hypervisor: kvm: Introduce Mutex around VcpuFd
This is required as the VcpuFd::run and VcpuFd::set_immediate_exit
methods now take a &mut self. I explored alternative solutions:

1. Using RefCell for runtime interior mutability - the Vcpu trait is
   Sync and it's not possible to use RefCell with types that are Sync.
2. Using UnsafeCell - the mutable reference nature of ::run and and
   ::set_kvm_immediate_exit was added for a reason so it unwise to
   bypass this.
3. Adjusting the trait interface to expose the &mut self - this requires
   an Arc<Mutex<>> around the hypervisor::vcpu::Vcpu object and was very
   intrusive.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
2024-04-25 20:53:53 +00:00
Rob Bradford
c022063ae8 hypervisor: Remove unused VmExit enum members
The members for {Io, Mmio}{Read, Write} are unused as instead exits of
those types are handled through the VmOps interface. Removing these is
also a prerequisite due to changes in the mutability of the
VcpuFd::run() method.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
2024-04-25 20:53:53 +00:00
Muminul Islam
512591ba1c hypervisor: rework VP state components
On Microsoft Hypervisor, we need to save/restore five
VP state components which are as follows:
    1. Local APIC
    2. Xsave
    3. Synthetic Message Page
    4. Synthetic Event Flags Page
    5. Synthetic Timers

In the MSHV crate we created a single struct for all the
components and API to get/set the states.

Signed-off-by: Muminul Islam <muislam@microsoft.com>
2024-04-24 16:02:54 +00:00
Ruslan Mstoi
5e9886bba4 build: add REUSE Compliance Check
In accordance with reuse requirements:
- Place each license file in the LICENSES/ directory
- Add missing SPDX-License-Identifier to files.
- Add .reuse/dep5 to bulk-license files

Fixes: #5887

Signed-off-by: Ruslan Mstoi <ruslan.mstoi@intel.com>
2024-04-19 17:35:45 +00:00
Nuno Das Neves
28d4957ba5 hypervisor: Remove redefinition of HV_PAGE_SIZE in mshv
HV_PAGE_SIZE is defined as a usize in mshv_bindings.
Remove the redefinition, and perform casts where necessary.

Signed-off-by: Nuno Das Neves <nudasnev@microsoft.com>
2024-03-29 13:14:37 -07:00
Jinank Jain
f0be099461 hypervisor: mshv: Add missing prototype of struct Vcpu for MshvVcpu
These are required while compiling for target aarch64.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-26 16:18:06 +00:00
Jinank Jain
3f95ada71e hypervisor: mshv: Add missing prototype of struct Vm for MshvVm
These functions are required when compiling for aarch64.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-26 16:18:06 +00:00
Jinank Jain
58e6a289ab hypervisor: mshv: Restrict MshvEmulator to x86
Current MSHV emulator only works for x86 instruction decoder. So, let's
restrict its usage to x86.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-23 17:20:18 +00:00
Jinank Jain
7c6c45128d hypervisor: mshv: Move ClockData under x86 feature flag
ClockData enum is only defined for x86_64 architecture so let's use it
just for that.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-23 17:20:18 +00:00
Jinank Jain
fdcc8539cd hypervisor: Don't restrict logger crate to just x86
Even aarch64 subsystem of hypervisor crate can use logging so don't
restrict it just to x86.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-21 08:34:20 +00:00
Jinank Jain
f7b9a6e577 hypervisor: mshv: Restrict unmapped GPA exit to x86
Current instruction emulator can only decode x86 instructions. Thus,
restrict the exit handling for just x86 guests.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-21 08:34:20 +00:00
Jinank Jain
c9e989de6e hypervisor: mshv: Restrict IO port exit to x86
IO ports exits can only happen on a x86 guest.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-21 08:34:20 +00:00
Jinank Jain
2501426e47 hypervisor: mshv: Restrict APIC EOI message to x86
APIC controller is only available on x86 machine. ARM uses a different
interrupt controller so those exit messages won't happen for ARM guests.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-21 08:34:20 +00:00
Jinank Jain
dad1ab1227 hypervisor: mshv: Restrict NMI injection to x86
NMI injection is only supported on x86 architecture.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-21 08:34:20 +00:00
Jinank Jain
3a60c65369 hypervisor: mshv: Reduce the visbility of get_supported_cpuid to x86
Supported CPUID could only be fetched for x86_64 guests.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-20 09:49:48 +00:00
Jinank Jain
719cae217e hypervisor: mshv: Restrict MSR and CPUID visbility for MshvVcpu to x86
MSR and CPUID are limited to x86 architecture so, reduce the visbility
of these two members inside struct MshvVcpu to just x86 architecture.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-20 09:49:48 +00:00
Rob Bradford
c721c0d88f hypervisor: emulator: Remove unnecessary #![allow(unused_mut)]
clippy was flagging this up as a mixture of mixed attributes but that
attribute is no longer necessary

warning: item has both inner and outer attributes
   --> hypervisor/src/arch/x86/emulator/mod.rs:769:1
    |
769 | / #[cfg(test)]
770 | | mod tests {
771 | |     #![allow(unused_mut)]
    | |_________________________^
    |
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#mixed_attributes_style
    = note: `#[warn(clippy::mixed_attributes_style)]` on by default

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
2024-03-19 18:36:22 +00:00
Rob Bradford
1e3d21e504 hypervisor: kvm: aarch64: Remove redundant import
error: the item `kvm_bindings` is imported redundantly
Error:  --> hypervisor/src/kvm/aarch64/gic/mod.rs:9:18
  |
9 | use crate::kvm::{kvm_bindings, KvmVm};
  |                  ^^^^^^^^^^^^ the item `kvm_bindings` is already defined by prelude
  |
  = note: `-D unused-imports` implied by `-D warnings`
  = help: to override `-D warnings` add `#[allow(unused_imports)]`

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
2024-03-19 18:36:22 +00:00
Rob Bradford
72620295dc hypervisor: Remove empty doc comment
warning: empty doc comment
  --> hypervisor/src/hypervisor.rs:24:1
   |
24 | / ///
25 | | ///
   | |___^
   |
   = help: consider removing or filling it
   = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#empty_docs
   = note: `#[warn(clippy::empty_docs)]` on by default

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
2024-03-19 18:36:22 +00:00
Rob Bradford
67054bf78b hypervisor: Remove import of TryInto
This is already provided by the prelude.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
2024-03-19 18:36:22 +00:00
Jinank Jain
89ff0627e6 hypervisor: mshv: Reduce msrs visibility to x86_64
Model Specific Registers (MSRs) are usually available on x86
architecture. So, let's reduce the visibility of MSRs to just x86
architecture.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-19 17:52:01 +00:00
Muminul Islam
2d6287d159 hypervisor: Fix boot failure on SNP guest
Current version can't boot a SNP guest while using
more than one VCPU. It turns out that there is an
issue in the Snp AP creation process. We should be writing
to Software exitinfo1 instead of exitinfo2. This patch fixes
the issue and we can boot multi vcpu SNP guest.

Signed-off-by: Muminul Islam <muislam@microsoft.com>
2024-03-13 23:03:33 +00:00
Jinank Jain
cd116cb24f vmm: hypervisor: Add support for injecting NMI for MSHV guest
Currently, we only support injecting NMI for KVM guests but we can do
the same for MSHV guests as well to have feature parity.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-06 00:12:06 +00:00
Jinank Jain
da376a4b37 hypervisor: mshv: Add support to handle GPA Attribute Intercept
Microsoft Hypervisor raises this request to change the guest page
visibility in case of SEV-SNP guest.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Nuno Das Neves <nudasnev@microsoft.com>
2024-03-05 14:55:58 +00:00
Yi Wang
c72bf0b32d vmm: support injecting NMI
Inject NMI interrupt when needed, by call ioctl KVM_NMI.

Signed-off-by: Yi Wang <foxywang@tencent.com>
2024-03-04 10:02:38 +00:00
Jinank Jain
9b722bbcf6 hypervisor: mshv: Don't unregister ioevent in case of SEV-SNP guest
Since we don't register ioevents in case of SEV-SNP guests. Thus, we
should not unregister it as well.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-02-20 06:55:13 -08:00
Rob Bradford
adb318f4cd misc: Remove redundant "use" imports
With the nightly toolchain (2024-02-18) cargo check will flag up
redundant imports either because they are pulled in by the prelude on
earlier match.

Remove those redundant imports.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
2024-02-19 17:54:30 +00:00
Jinank Jain
d0be450b1b hypervisor: Do not register ioevent for SEV-SNP
... enabled VMs. IOEvents are not supported in case of SEV-SNP VMs. All
the IO events are delievered via GHCB protocol.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>
2024-02-13 11:26:20 -08:00
Jinank Jain
3a683b54d5 hypervisor: Add a flag to identify sev-snp VM
This will help in identify whether a VM supports sev-snp and based on
that disable/enable certain features.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>
2024-02-13 11:26:20 -08:00
Jinank Jain
321d6f47e6 hypervisor: mshv: Add new memory region flag
GPA_MAP_ADJUSTABLE suggests hypervisor to adjust GPA permissions as
required.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-02-13 09:08:59 +00:00
Jinank Jain
50241f94d9 hypervisor: mshv: Add support to handle unaccepted GPA
Unaccepted GPA is usually thrown by Microsoft hypervisor in case of
mismatch between GPA and GVA mappings. This is a fatal message from the
hypervisor perspective so we would need to error out from the vcpu run
loop. Along with add some debug message to identify the broken mapping
between GVA and GPA.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>
2024-02-07 11:00:00 -08:00
Bo Chen
3ce0fef7fd build: Bump vmm-sys-util crate and its consumers
This patch bumps the following crates, including `kvm-bindings@0.7.0`*,
`kvm-ioctls@0.16.0`**, `linux-loader@0.11.0`, `versionize@0.2.0`,
`versionize_derive@0.1.6`***, `vhost@0.10.0`,
`vhost-user-backend@0.13.1`, `virtio-queue@0.11.0`, `vm-memory@0.14.0`,
`vmm-sys-util@0.12.1`, and the latest of `vfio-bindings`, `vfio-ioctls`,
`mshv-bindings`,`mshv-ioctls`, and `vfio-user`.

* A fork of the `kvm-bindings` crate is being used to support
serialization of various structs for migration [1]. Also, code changes
are made to accommodate the updated `struct xsave` from the Linux
kernel. Note: these changes related to `struct xsave` break
live-upgrade.

** The new `kvm-ioctls` crate introduced breaking changes for
the `get/set_one_reg` API on `aarch64` [2], so code changes are made to
the new APIs.

*** A fork of the `versionize_derive` crate is being used to support
versionize on packed structs [3].

[1] https://github.com/cloud-hypervisor/kvm-bindings/tree/ch-v0.7.0
[2] https://github.com/rust-vmm/kvm-ioctls/pull/223
[3] https://github.com/cloud-hypervisor/versionize_derive/tree/ch-0.1.6

Fixes: #6072

Signed-off-by: Bo Chen <chen.bo@intel.com>
2024-01-25 10:14:54 +00:00
Muminul Islam
5368ff28da hypervisor: Add api to set sev control register
This register configures the SEV feature control
state on a virtual processor.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>
2024-01-24 14:32:16 -08:00
Rob Bradford
3993663e5c hypervisor: kvm: Import TDX vmcall structure
Consistent with the other data structures and constants used in TDX
support code import the necessary structures from the kernel for
accessing the vmcall structure.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
2024-01-24 11:02:05 -08:00
Muminul Islam
cbcbf635ab hypervisor: use right size of host_data
Use right and exact size 32 bytes for host data field
for completing the isolated import. This way OOB
can be avoided during a function call.

Signed-off-by: Muminul Islam <muislam@microsoft.com>
2024-01-08 15:55:39 -08:00
Muminul Islam
7d5ea5ca37 hypervisor: fix few typos and cosmetic issues
This patch adds missing new lines after functions,
fixes few typos in the comments, adds few missing
comments to SNP related functions.

Signed-off-by: Muminul Islam <muislam@microsoft.com>
2023-12-12 14:42:22 +00:00
Muminul Islam
ec79820b3f hypervisor: Add api to retrieve CPUID leaf
Add necessary API to retrieve cpuid leaf on MSHV.
This API is used to update cpuid information
during the parsing of the igvm file.

Microsoft hypervisor does not provide common
CpuID like KVM. That's why we need to call this API
during the IGVM parsing.

Signed-off-by: Muminul Islam <muislam@microsoft.com>
2023-12-08 09:22:42 -08:00
Jinank Jain
84b643f80b hypervisor: Add support to bringup AP threads for SEV-SNP guest
As part SMP bringup for a SEV-SNP guest, BSP sets up the VMSA page for
each AP threads and informs hypervisor about the same using a VMGEXIT.
Thus, extend the current GHCB interface to handle this scenario.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2023-11-16 14:58:53 -08:00
Jinank Jain
d7d6054b8c hypervisor: Add support for handling SNP guest request
SEV-SNP guest can request AMD's secure co-processor i.e., PSP to
generate an runtime attesation report. During this process guest needs
to inform PSP about the request and response GPAs where that report
would be generated by the PSP. This is handled via a VMGEXIT request.
Thus, extend the current GHCB handling to add support for it.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2023-11-16 14:58:53 -08:00
Jinank Jain
96bc282759 hypervisor: mshv: Add VmFd to MshvVcpu struct
This would be required later to implement few additional operations on
top of it.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2023-11-16 14:58:53 -08:00
Jinank Jain
0287e6a603 hypervisor: Add support for MMIO write emulation
This is very similar MMIO read emulation for SEV-SNP guest.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>
2023-10-30 10:23:52 -07:00
Jinank Jain
ac43825f79 hypervisor: Add support MMIO read VMGEXIT
MMIO emulation is also performed via VMGEXIT in case of SEV-SNP guest.
Emulation is done in a very similar way like a regular guest. Just need
to make sure that guest memory is access via read/write GPA hypercall
instead of directly accessing it.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>
2023-10-30 10:23:52 -07:00
Jinank Jain
7975207e0f hypervisor: Add support for legacy I/O port emulation
Legacy port emulation requires reading RAX register from GHCB page for
SEV-SNP guest. This is the major difference between a regular guest and
SEV-SNP enabled guest.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>
2023-10-30 10:23:52 -07:00
Jinank Jain
e2288a8d2c hypervisor: Add support for handling extended guest request
Currently MSHV does not support fetching extended guest report and thus
return an appropriate error stating the NAE event is not valid.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Nuno Das Neves <nudasnev@microsoft.com>
2023-10-30 10:23:52 -07:00
Jinank Jain
cb5ea05945 hypervisor: Add support for handling #HV Doorbell Page
As part of this handling there are 4 different operations:

1. Getting the hypervisor preffered doorbell page GPA.
2. Informing hypervisor about the doorbell page chosen by the guest
3. Querying the GPA of the doorbell page
4. Clearing the GPA of the doorbell page from hypervisor

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>
2023-10-30 10:23:52 -07:00
Jinank Jain
d68fec594e hypervisor: Add support for handling SEV INFO request
As part of handling this request, hypervisor is expected to three
things:

1. Maximum GHCB protocol version supported.
2. Minimum GHCB protocol version supported.
3. SEV-page table encryption bit number.

If the guest cannot support the protocol range supplied by the
hypervisor, it should terminate

Signed-off-by: Muminul Islam <muislam@microsoft.com>
Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2023-10-30 10:23:52 -07:00
Jinank Jain
6f4d82bd61 hypervisor: Add support for registering GHCB GPA with hypervisor
SEV-SNP guest allocates a GHCB page and in order to update hypervisor
about the same, there is a vmgexit which allows registering GHCB page
with the hypervisor.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>
2023-10-30 10:23:52 -07:00