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719cae217e
cloud-hypervisor/hypervisor/src
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Jinank Jain 719cae217e hypervisor: mshv: Restrict MSR and CPUID visbility for MshvVcpu to x86 
MSR and CPUID are limited to x86 architecture so, reduce the visbility
of these two members inside struct MshvVcpu to just x86 architecture.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2024-03-20 09:49:48 +00:00
..
arch hypervisor: emulator: Remove unnecessary #![allow(unused_mut)] 2024-03-19 18:36:22 +00:00
kvm hypervisor: kvm: aarch64: Remove redundant import 2024-03-19 18:36:22 +00:00
mshv hypervisor: mshv: Restrict MSR and CPUID visbility for MshvVcpu to x86 2024-03-20 09:49:48 +00:00
cpu.rs vmm: hypervisor: Add support for injecting NMI for MSHV guest 2024-03-06 00:12:06 +00:00
device.rs
hypervisor.rs hypervisor: Remove empty doc comment 2024-03-19 18:36:22 +00:00
lib.rs
vm.rs